Cover Ring for Use in Semiconductor Processing Chamber

FIG. 1 is a bottom isometric view of a cover ring for use in a semiconductor processing chamber in accordance with some embodiments.

FIG. 2 is a top plan view thereof.

FIG. 3 is a bottom plan view thereof.

FIG. 4 is a front elevation view thereof.

FIG. 5 is a back elevation view thereof.

FIG. 6 is a right side elevation view thereof; and,

FIG. 7 is a left side elevation view thereof.

The broken lines in the drawings illustrate portions of the cover ring for use in a semiconductor processing chamber that form no part of the claimed design.