- US12244518utility2025Network-on-chip Architecture for Handling Different Data Sizes0 cites
- US12235671utility2025Adding Soft Logic to Flush a Pipeline and Reduce Current Ramp0 cites
- US12235782utility2025Noc Routing in a Multi-chip Device0 cites
- US12235950utility2025Hierarchical Hardware-software Partitioning and Configuration0 cites
- US12237287utility2025Chip Bump Interface Compatible with Different Orientations and Types of Devices0 cites
- US12237829utility2025Source Follower Circuitry Including Phase Shift Circuitry0 cites
- US12231532utility2025Scalable Tweak Engines and Prefetched Tweak Values for Encyrption Engines0 cites
- US12223355utility2025Synchronization of System Resources in a Multi-socket Data Processing System0 cites
- US12224954utility2025Network Interface Device0 cites
- US12204940utility2025Transparent and Remote Kernel Execution in a Heterogeneous Computing System0 cites
- US12200087utility2025Dynamic Data Conversion for Network Computer Systems0 cites
- US12190077utility2025Method and Apparatus for Eliminating Inter-link Skew in High-speed Serial Data Communications0 cites
- US12190994utility2025Single Port Memory with Multiple Memory Operations per Clock Cycle0 cites
- US12191876utility2025Gain Calibration with Quantizer Offset Settings0 cites
- US12182552utility2024Splitting Vector Processing Loops with an Unknown Trip Count0 cites
- US12183311utility2024Clock Recovery Circuit0 cites
- US12175622utility2024Smart Cache Implementation for Image Warping0 cites
- US12176896utility2024Programmable Stream Switches and Functional Safety Circuits in Integrated Circuits0 cites
- US12176900utility2024Buffer Circuitry Having Improved Bandwidth and Return Loss0 cites
- US12164451utility2024Data Processing Array Interface Having Interface Tiles with Multiple Direct Memory Access Circuits0 cites