Patents/Assignees

Ventana Micro Systems Inc.

74 patents in portfolio

US12020032utility2024
Prediction Unit That Provides a Fetch Block Descriptor Each Clock Cycle
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US12014178utility2024
Folded Instruction Fetch Pipeline
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US12014180utility2024
Dynamically Foldable and Unfoldable Instruction Fetch Pipeline
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US12008375utility2024
Branch Target Buffer That Stores Predicted Set Index and Predicted Way Number of Instruction Cache
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US12001337utility2024
Using Physical Address Proxies to Accomplish Penalty-less Processing of Load/store Instructions Whose Data Straddles Cache Line Address Boundaries
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US12001843utility2024
Microprocessor Including a Decode Unit That Performs Pre-execution of Load Constant Micro-operations
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US11989285utility2024
Thwarting Store-to-load Forwarding Side Channel Attacks by Pre-forwarding Matching of Physical Address Proxies And/or Permission Checking
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US11989286utility2024
Conditioning Store-to-load Forwarding (STLF) on Past Observations of STLF Propriety
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US11977893utility2024
Folded Instruction Fetch Pipeline
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US11934519utility2024
Conditioning Store-to-load Forwarding (STLF) on Past Observations of STLF Propriety
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US11907369utility2024
Processor That Mitigates Side Channel Attacks by Preventing Cache Memory State from Being Affected by a Missing Load Operation by Inhibiting or Canceling a Fill Request of the Load Operation If an Older Load Generates a Need for an Architectural Exception
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US11880685utility2024
Folded Instruction Fetch Pipeline
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US11868263utility2024
Using Physical Address Proxies to Handle Synonyms When Writing Store Data to a Virtually-indexed Cache
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US11868469utility2024
Processor That Mitigates Side Channel Attacks by Preventing All Dependent Instructions from Consuming Architectural Register Result Produced by Instruction That Causes a Need for an Architectural Exception
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US11860794utility2024
Generational Physical Address Proxies
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US11853424utility2023
Processor That Mitigates Side Channel Attacks by Refraining from Allocating an Entry in a Data TLB for a Missing Load Address When the Load Address Misses Both in a Data Cache Memory and in the Data TLB and the Load Address Specifies a Location Without a Valid Address Translation or Without Permission to Read from the Location
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US11841802utility2023
Microprocessor That Prevents Same Address Load-load Ordering Violations
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US11836080utility2023
Physical Address Proxy (PAP) Residency Determination for Reduction of PAP Reuse
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US11836498utility2023
Single Cycle Predictor
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US11816489utility2023
Microprocessor with Prediction Unit Pipeline That Provides a Next Fetch Address at a Rate of One per Clock Cycle
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