Patents/Assignees

Ventana Micro Systems Inc.

74 patents in portfolio

US11809560utility2023
Processor That Mitigates Side Channel Attacks by Refraining from Allocating an Entry in a Data TLB for a Missing Load Address When the Load Address Misses Both in a Data Cache Memory and in the Data TLB and the Load Address Specifies a Location Without a Valid Address Translation or Without Permission to Read from the Location
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US11803637utility2023
Microprocessor That Prevents Store-to-load Forwarding Between Different Translation Contexts
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US11803638utility2023
Microprocessor Core with a Store Dependence Predictor Accessed Using a Translation Context
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US11803640utility2023
Processor That Mitigates Side Channel Attacks by Preventing Cache Memory State from Being Affected by a Missing Load Operation by Inhibiting or Canceling a Fill Request of the Load Operation If an Older Load Generates a Need for an Architectural Exception
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US11797673utility2023
Processor That Mitigates Side Channel Attacks by Expeditiously Initiating Flushing of Instructions Dependent Upon a Load Instruction That Causes a Need for an Architectural Exception
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US11789871utility2023
Microprocessor That Prevents Same Address Load-load Ordering Violations
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US11762999utility2023
Processor That Mitigates Side Channel Attacks by Refraining from Allocating an Entry in a Data TLB for a Missing Load Address When the Load Address Misses Both in a Data Cache Memory and in the Data TLB and the Load Address Specifies a Location Without a Valid Address Translation or Without Permission to Read from the Location
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US11755731utility2023
Processor That Prevents Speculative Execution Across Translation Context Change Boundaries to Mitigate Side Channel Attacks
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US11755732utility2023
Microprocessor That Conditions Store-to-load Forwarding on Circumstances Associated with a Translation Context Update
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US11733972utility2023
Processor That Mitigates Side Channel Attacks by Providing Random Load Data as a Result of Execution of a Load Operation That Does Not Have Permission to Access a Load Address
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US11734426utility2023
Processor That Mitigates Side Channel Attacks by Prevents Cache Line Data Implicated by a Missing Load Address from Being Filled Into a Data Cache Memory When the Load Address Specifies a Location with No Valid Address Translation or No Permission to Read from the Location
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US11687466utility2023
Translation Lookaside Buffer Consistency Directory for Use with Virtually-indexed Virtually-tagged First Level Data Cache That Holds Page Table Permissions
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US11625479utility2023
Virtually-tagged Data Cache Memory That Uses Translation Context to Make Entries Allocated During Execution Under One Translation Context Inaccessible During Execution Under Another Translation Context
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US11620377utility2023
Physically-tagged Data Cache Memory That Uses Translation Context to Reduce Likelihood That Entries Allocated During Execution Under One Translation Context Are Accessible During Execution Under Another Translation Context
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