Patents/Assignees

Synopsys, Inc.

423 patents in portfolio

US11941379utility2024
Accelerating Static Program Analysis with Artifact Reuse
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US11937507utility2024
Power Harvesting for Integrated Circuits
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US11928024utility2024
Atomic Correction of Single Bit Errors Within a Memory
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US11922106utility2024
Memory Efficient Scalable Distributed Static Timing Analysis Using Structure Based Self-aligned Parallel Partitioning
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US11921160utility2024
Using Scan Chains to Read Out Data from Integrated Sensors During Scan Tests
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US11914939utility2024
Clock Re-convergence Pessimism Removal Through Pin Sharing During Clock Tree Planning
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US11914306utility2024
Predicting Defect Rate Based on Lithographic Model Parameters
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US11915984utility2024
Forming a Wrap-around Contact to Connect a Source or Drain Epitaxial Growth of a Complimentary Field Effect Transistor (CFET) to a Buried Power Rail (BPR) of the CFET
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US11907631utility2024
Reset Domain Crossing Detection and Simulation
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US11907088utility2024
Testing of Hardware Queue Systems Using on Device Test Generation
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US11907630utility2024
Power Validation Based on Power Assertion Specification
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US11900042utility2024
Stochastic-aware Lithographic Models for Mask Synthesis
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US11899586utility2024
Energy Efficient Tag Partitioning in Cache Memory
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US11894049utility2024
CFET SRAM Cell Utilizing 8 Transistors
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US11893332utility2024
Global Mistracking Analysis in Integrated Circuit Design
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US11874597utility2024
Stochastic Optical Proximity Corrections
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US11876516utility2024
Non-fighting Level Shifters
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US11868694utility2024
System and Method for Optimizing Emulation Throughput by Selective Application of a Clock Pattern
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US11868696utility2024
Lightweight Unified Power Format Implementation for Emulation and Prototyping
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US11863187utility2024
D-type Wholly Dissimilar High-speed Static Set-reset Flip Flop
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