Patents/Assignees

Ventana Micro Systems Inc.

74 patents in portfolio

US12566702utility2026
Physical Address Proxy Reuse Management
0 cites
US12560993utility2026
Power Management of Devices with Differentiated Power Scaling Based on Relative Power Benefit Estimation
0 cites
US12498926utility2025
Microprocessor That Builds Consistent Loop Iteration Count Unrolled Loop Multi-fetch Block Macro-op Cache Entries
0 cites
US12498927utility2025
Microprocessor That Allows Same-fetch Block Start Address Co-residence of Unrolled Loop Multi-fetch Block Macro-op Cache Entry and Loop Body Macro-op Cache Entry Used to Build Same
0 cites
US12498928utility2025
Microprocessor That Builds Multi-fetch Block Macro-op Cache Entries in Two-stage Process
0 cites
US12498929utility2025
Microprocessor That Performs Partial Fallback Abort Processing of Multi-fetch Block Macro-op Cache Entries
0 cites
US12498933utility2025
Prediction Unit That Predicts Successor Fetch Block Start Address of Multi-fetch Block Macro-op Cache Entry
0 cites
US12499050utility2025
Physical Address Proxy (PAP) Residency Determination for Reduction of PAP Reuse
0 cites
US12493466utility2025
Microprocessor That Builds Inconsistent Loop That Iteration Count Unrolled Loop Multi-fetch Block Macro-op Cache Entries
0 cites
US12493468utility2025
Microprocessor That Performs Mid-macro-op Cache Entry Restart Abort Processing
0 cites
US12493469utility2025
Microprocessor That Extends Sequential Multi-fetch Block Macro-op Cache Entries
0 cites
US12493558utility2025
Using Physical Address Proxies to Accomplish Penalty-less Processing of Load/store Instructions Whose Data Straddles Cache Line Address Boundaries
0 cites
US12487830utility2025
Prediction Unit with First Predictor That Provides a Hashed Fetch Address of a Current Fetch Block to Its Own Input and to a Second Predictor That Uses It to Predict the Fetch Address of a Next Fetch Block
0 cites
US12487926utility2025
Prediction Unit That Predicts Branch History Update Information Produced by Multi-fetch Block Macro-op Cache Entry
0 cites
US12487936utility2025
Store-to-load Forwarding Correctness Checks Using Physical Address Proxies Stored in Load Queue Entries
0 cites
US12487939utility2025
Virtually-indexed Cache Coherency Using Physical Address Proxies
0 cites
US12481310utility2025
Method and Apparatus for Deskewing Die to Die Communication Between System on Chip Devices
0 cites
US12450066utility2025
Microprocessor That Builds Sequential Multi-fetch Block Macro-op Cache Entries
0 cites
US12450067utility2025
Microprocessor That Performs Selective Multi-fetch Block Macro-op Cache Entry Invalidation
0 cites
US12393426utility2025
Store-to-load Forwarding Correctness Checks at Store Instruction Commit
0 cites

Page 1 of 4Next →