- US11726899utility2023Waveform Based Reconstruction for Emulation0 cites
- US11720015utility2023Mask Synthesis Using Design Guided Offsets0 cites
- US11714117utility2023Automated Method to Check Electrostatic Discharge Effect on a Victim Device0 cites
- US11710634utility2023Fabrication Technique for Forming Ultra-high Density Integrated Circuit Components0 cites
- US11709984utility2023Automatic Sequential Retry on Compilation Failure0 cites
- US11704471utility2023Three-dimensional Mask Simulations Based on Feature Images0 cites
- US11705986utility2023Hardware Based Cyclic Redundancy Check (CRC) Re-calculator for Timestamped Frames Over a Data Bus0 cites
- US11704467utility2023Automated Balanced Global Clock Tree Synthesis in Multi Level Physical Hierarchy0 cites
- US11694010utility2023Reformatting Scan Patterns in Presence of Hold Type Pipelines0 cites
- US11694016utility2023Fast Topology Bus Router for Interconnect Planning0 cites
- US11681842utility2023Latency Offset in Pre-clock Tree Synthesis Modeling0 cites
- US11681848utility2023On-the-fly Multi-bit Flip Flop Generation0 cites
- US11675726utility2023Interconnect Repeater Planning and Implementation Flow for Abutting Designs0 cites
- US11669665utility2023Application-specific Integrated Circuit (ASIC) Synthesis Based on Lookup Table (LUT) Mapping and Optimization0 cites
- US11669667utility2023Automatic Test Pattern Generation (ATPG) for Parametric Faults0 cites
- US11670361utility2023Sequential Delay Enabler Timer Circuit for Low Voltage Operation for Srams0 cites
- US11665031utility2023Tuning Analog Front End Response for Jitter Tolerance Margins0 cites
- US11663485utility2023Classification of Patterns in an Electronic Circuit Layout Using Machine Learning Based Encoding0 cites
- US11663384utility2023Timing Modeling of Multi-stage Cells Using Both Behavioral and Structural Models0 cites
- US11662383utility2023High-speed Functional Protocol Based Test and Debug0 cites