- US12248401utility2025Eviction Operations Based on Eviction Message Types of Different Priorities0 cites
- US12248405utility2025Address Boundary Functions for Physical and Localized Addresses0 cites
- US12235749utility2025Trace Encoder with Event Filter0 cites
- US12223323utility2025Out-of-order Vector Iota Calculations0 cites
- US12210874utility2025Processing for Vector Load or Store Micro-operation with Inactive Mask Elements0 cites
- US12204458utility2025Translation Lookaside Buffer Probing Prevention0 cites
- US12204462utility2025Downgrading a Permission Associated with Data Stored in a Cache0 cites
- US12197335utility2025Canceling Prefetch of Cache Blocks Based on an Address and a Bit Field0 cites
- US12189544utility2025Transmitting a Response with a Request and State Information About the Request0 cites
- US12086004utility2024Selectable and Hierarchical Power Management0 cites
- US12086067utility2024Load-store Pipeline Selection for Vectors0 cites
- US12066941utility2024Method for Executing Atomic Memory Operations When Contested0 cites
- US11966290utility2024Checker Cores for Fault Tolerant Processing0 cites
- US11922101utility2024Integrated Circuits as a Service0 cites
- US11914933utility2024Generation of Dynamic Design Flows for Integrated Circuits0 cites
- US11861365utility2024Macro-op Fusion0 cites
- US11847060utility2023Data Cache with Prediction Hints for Cache Hits0 cites
- US11797308utility2023Fetch Stage Handling of Indirect Jumps in a Processor Pipeline0 cites
- US11748536utility2023Automated Microprocessor Design0 cites
- US11687342utility2023Way Predictor and Enable Logic for Instruction Tightly-coupled Memory and Instruction Cache0 cites