- US12399837utility2025Translation Lookaside Buffer (TLB) Prefetcher with Multi-level TLB Prefetches and Feedback Architecture0 cites
- US12386764utility2025Selective Transfer of Data Including a Priority Byte0 cites
- US12373210utility2025Transfer Buffer Between a Scalar Pipeline and Vector Pipeline0 cites
- US12367154utility2025Logging Guest Physical Address for Memory Access Faults0 cites
- US12367047utility2025Debug Trace Circuitry Configured to Generate a Record Including an Address Pair and a Counter Value0 cites
- US12346187utility2025Systems and Methods for Clock Gating0 cites
- US12346268utility2025Address Range Encoding in System on a Chip with Securely Partitioned Memory Space0 cites
- US12340226utility2025Vector Instruction Cracking After Scalar Dispatch0 cites
- US12332799utility2025Speculative Request Indicator in Request Message0 cites
- US12332733utility2025Determining an Error Handling Mode0 cites
- US12314191utility2025Memory Protection for Vector Operations0 cites
- US12314718utility2025Stalling Issue Queue Entries Until Consecutive Allocated Entries Are Available for Segmented Stores0 cites
- US12314715utility2025Tracking of Store Operations0 cites
- US12306772utility2025Orderability of Operations0 cites
- US12293192utility2025Bundling and Dynamic Allocation of Register Blocks for Vector Instructions0 cites
- US12271309utility2025Relative Age Tracking for Entries in a Buffer0 cites
- US12265829utility2025Re-triggering Wake-up to Handle Time Skew Between Scalar and Vector Sides0 cites
- US12259825utility2025Concurrent Support for Multiple Cache Inclusivity Schemes Using Low Priority Evict Operations0 cites
- US12260217utility2025Using Renamed Registers to Support Multiple Vset{i}vl{i} Instructions0 cites
- US12253959utility2025Memory Protection for Gather-scatter Operations0 cites