Patents/Assignees

SANDISK TECHNOLOGIES LLC

401 patents in portfolio

US11894037utility2024
First Fire and Cold Start in Memories with Threshold Switching Selectors
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US11894051utility2024
Temperature-dependent Word Line Voltage and Discharge Rate for Refresh Read of Non-volatile Memory
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US11894056utility2024
Non-volatile Memory with Efficient Word Line Hook-up
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US11894080utility2024
Time-tagging Read Levels of Multiple Wordlines for Open Block Data Retention
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US11894062utility2024
Semi-circle Drain Side Select Gate Maintenance by Selective Semi-circle Dummy Word Line Program
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US11894064utility2024
Sub-block Mode for Non-volatile Memory
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US11894067utility2024
Method to Fix Cumulative Read Induced Drain Side Select Gate Downshift in Memory Apparatus with On-pitch Drain Side Select Gate
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US11894071utility2024
Non-volatile Memory with Differential Temperature Compensation for Bulk Programming
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US11887677utility2024
Quick Pass Write Programming Techniques in a Memory Device
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US11887670utility2024
Controlling Bit Line Pre-charge Voltage Separately for Multi-level Memory Cells and Single-level Memory Cells to Reduce Peak Current Consumption
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US11887674utility2024
Utilizing Data Pattern Effect to Control Read Clock Timing and Bit Line Kick for Read Time Reduction
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US11889684utility2024
Three-dimensional Memory Device with Separated Source-side Lines and Method of Making the Same
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US11889694utility2024
Three-dimensional Memory Device with Separated Contact Regions and Methods for Forming the Same
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US11882702utility2024
Lateral Transistors for Selecting Blocks in a Three-dimensional Memory Array and Methods for Forming the Same
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US11881266utility2024
Neighbor Bit Line Coupling Enhanced Gate-induced Drain Leakage Erase for Memory Apparatus with On-pitch Semi-circle Drain Side Select Gate Technology
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US11882706utility2024
One Selector One Resistor MRAM Crosspoint Memory Array Fabrication Methods
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US11881271utility2024
Non-volatile Memory with Engineered Channel Gradient
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US11875043utility2024
Loop Dependent Word Line Ramp Start Time for Program Verify of Multi-level NAND Memory
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US11875842utility2024
Systems and Methods for Staggering Read Operation of Sub-blocks
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US11877446utility2024
Three-dimensional Memory Device with Electrically Conductive Layers Containing Vertical Tubular Liners and Methods for Forming the Same
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