- US11996167utility2024Generating Random Addresses for Nonvolatile Storage of Sensitive Data0 cites
- US11994930utility2024Optimizing Power in a Memory Device0 cites
- US11996160utility2024Low Power Signaling Interface0 cites
- US11996164utility2024Low Power Memory Control with On-demand Bandwidth Boost0 cites
- US11990177utility2024Multi-die Memory Device0 cites
- US11990912utility2024Data Transmission Using Delayed Timing Signals0 cites
- US11989609utility2024Method of Securing a Comparison of Data During the Execution of a Program0 cites
- US11989430utility2024Memory Module with Persistent Calibration0 cites
- US11983137utility2024Memory System with Independently Adjustable Core and Interface Data Rates0 cites
- US11983031utility2024Drift Detection in Timing Signal Forwarded from Memory Controller to Memory Device0 cites
- US11977442utility2024Serial Presence Detect Reliability0 cites
- US11972121utility2024Load-reduced DRAM Stack0 cites
- US11973153utility2024Synchronous Wired-or ACK Status for Memory with Variable Write Latency0 cites
- US11967364utility2024Variable Width Memory Module Supporting Enhanced Error Detection and Correction0 cites
- US11960418utility2024Semiconductor Memory Systems with On-die Data Buffering0 cites
- US11960344utility2024Memory Controller with Looped-back Calibration Data Receiver0 cites
- US11960438utility2024Methods and Circuits for Streaming Data to Processing Elements in Stacked Processor-plus-memory Architecture0 cites
- US11963299utility2024Load Reduced Memory Module0 cites
- US11953934utility2024Memory System Using Asymmetric Source-synchronous Clocking0 cites
- US11953981utility2024Memory Module Register Access0 cites