Patents/Assignees

Cadence Design Systems, Inc.

223 patents in portfolio

US11876521utility2024
Dynamically Updated Delay Line
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US11876650utility2024
Multi-stage Equalizer for Inter-symbol Interference Cancellation
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US11868241utility2024
Method and System for Optimizing a Verification Test Regression
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US11868695utility2024
Driver Resizing Using a Transition-based Pin Capacitance Increase Margin
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US11868698utility2024
Context-aware Circuit Design Layout Construct
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US11868786utility2024
Systems and Methods for Distributed and Parallelized Emulation Processor Configuration
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US11861277utility2024
System and Method for Routing in an Electronic Design
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US11861452utility2024
Quantized Softmax Layer for Neural Networks
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US11861492utility2024
Quantizing Trained Neural Networks with Removal of Normalization
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US11847392utility2023
Method, Product, and System for Dynamic Design Switching for High Performance Mixed Signal Simulation
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US11842130utility2023
Model-based Simulation Result Predictor for Circuit Design
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US11829241utility2023
Serializing and Deserializing Stage Testing
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US11829276utility2023
System and Method for Monitoring Compliance Patterns
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US11829852utility2023
System, Method, and Computer Program Product for Predicting Pin Placement in an Electronic Design
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US11831153utility2023
High-bandwidth Signal Driver/receiver
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US11831315utility2023
Low Power Current Mode Logic
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US11831323utility2023
Methods and Circuits for Reducing Clock Jitter
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US11831474utility2023
Methods and Circuits for Decision-feedback Equalization Using Compensated Decision Regions
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US11823018utility2023
Method, Product, and Apparatus for a Machine Learning Process Using Weight Sharing Within a Systolic Array Having Reduced Memory Bandwidth
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US11811362utility2023
Voltage Controlled Oscillator (VCO) with Adaptive Temperature Compensation
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