Base for a Multi-chamber Semiconductor

FIG. 1 is a top, front, and right side perspective view of a base for a multi-chamber semiconductor, showing our new design;

FIG. 2 is a front elevational view thereof;

FIG. 3 is a rear elevational view thereof;

FIG. 4 is a left side elevation view thereof;

FIG. 5 is a right side elevation view thereof;

FIG. 6 is a top plan view thereof;

FIG. 7 is a bottom plan view thereof; and,

FIG. 8 is an enlarged view of encircled portion “ 8 ” in FIG. 1 .

The broken lines in the drawings illustrate portions of a base for a multi-chamber semiconductor which form no part of the claimed design.

The dashed dot line showing the boundary of the enlarged portion view of FIG. 8 in FIGS. 1 and 8 form no part of the claimed design.