5 Patents
- US123410192025Anti-oxidation Layer to Prevent Dielectric Loss from Planarization Process
Taiwan Semiconductor Manufacturing Company, Ltd.
0 cites - US121912502025Method of Forming Bottom Electrode via for Memory Device
Taiwan Semiconductor Manufacturing Company, Ltd.
0 cites - US121070042024In-situ CMP Self-assembled Monolayer for Enhancing Metal-dielectric Adhesion and Preventing Metal Diffusion
Taiwan Semiconductor Manufacturing Co., Ltd.
0 cites - US118548222023Anti-oxidation Layer to Prevent Dielectric Loss from Planarization Process
Taiwan Semiconductor Manufacturing Company, Ltd.
0 cites - US118108172023In-situ CMP Self-assembled Monolayer for Enhancing Metal-dielectric Adhesion and Preventing Metal Diffusion
Taiwan Semiconductor Manufacturing Co., Ltd.
0 cites