Zhe-wei Jiang

7 Patents

• US126140152026

  System and Method for Transistor Placement in Standard Cell Layout

  Taiwan Semiconductor Manufacturing Company, Ltd.

  0 cites
• US122108112025

  Layout Context-based Cell Timing Characterization

  TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY Ltd.

  0 cites
• US121060332024

  Metal Cut Optimization for Standard Cells

  Taiwan Semiconductor Manufacturing Co., Ltd.

  0 cites
• US120731622024

  Capacitive Isolation Structure Insert for Reversed Signals

  TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, Ltd.

  0 cites
• US119076332024

  Layout for Integrated Circuit and the Integrated Circuit

  TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY Ltd.

  0 cites
• US118536762023

  Layout Context-based Cell Timing Characterization

  TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY Ltd.

  0 cites
• US117344812023

  Metal Cut Optimization for Standard Cells

  Taiwan Semiconductor Manufacturing Co., Ltd.

  0 cites