11 Patents
- US124023842025Standard Cell Design with Dummy Padding
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, Ltd.
0 cites - US122294892025System and Method of Verifying Slanted Layout Components
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, Ltd.
0 cites - US121311092024Block Level Design Method for Heterogeneous Pg-structure Cells
Taiwan Semiconductor Manufacturing Co., Ltd.
0 cites - US120083022024Integrated Circuit with Thicker Metal Lines on Lower Metallization Layer
TAIWAN SEMICONDUCTOR MANUFACTURING CO., Ltd.
0 cites - US118612882024System and Method of Verifying Slanted Layout Components
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, Ltd.
0 cites - US118536782023Block Level Design Method for Heterogeneous Pg-structure Cells
Taiwan Semiconductor Manufacturing Co., Ltd.
0 cites - 0 cites
- 0 cites
- US115935462023Integrated Circuit with Thicker Metal Lines on Lower Metallization Layer
TAIWAN SEMICONDUCTOR MANUFACTURING CO., Ltd.
0 cites - US115741062023Method, System, and Storage Medium of Resource Planning for Designing Semiconductor Device
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY Ltd.
0 cites - US115741082023Block Level Design Method for Heterogeneous Pg-structure Cells
Taiwan Semiconductor Manufacturing Co., Ltd.
0 cites