Patents/Inventors

Yu-chung Lien

San Jose, CAUS57 patents

50 Patents

US126145932026
Managing Allocation of Blocks in a Memory Sub-system
Micron Technology, Inc.
0 cites
US126021692026
Reliability Gain in Memory Devices with Adaptively Selected Erase Policies
Micron Technology, Inc.
0 cites
US125974762026
Program Verify Compensation in a Memory Device with a Defective Deck
Micron Technology, Inc.
0 cites
US125800312026
Level-based Data Refresh in a Memory Sub-system
Micron Technology, Inc.
0 cites
US125674682026
Pass Voltage Adjustment for Program Operation in a Memory Device with a Defective Deck
Micron Technology, Inc.
0 cites
US125610722026
Corrective Read with Parallel Auto-read Calibration in a Memory Sub-system
Micron Technology, Inc.
0 cites
US125413112026
Power Management for Memory Devices with Partially Good Blocks
MICRON TECHNOLOGY, Inc.
0 cites
US125370682026
Half Good Block Handling with Defective Deck Pre-programing in a Memory Sub-system
Micron Technology, Inc.
0 cites
US125370602026
Programming Delay Scheme for in a Memory Sub-system Based on Memory Reliability
Micron Technology, Inc.
0 cites
US124501542025
Selection of Erase Policy in a Memory Device
Micron Technology, Inc.
0 cites
US124170282025
Dynamic Erase Operation Selection Using Erase Policy
MICRON TECHNOLOGY, Inc.
0 cites
US124178082025
Single-level Cell Programming with Adaptive Wordline Ramp Rate
Micron Technology, Inc.
0 cites
US124170262025
Adaptive Sensing Time for Memory Operations
MICRON TECHNOLOGY, Inc.
0 cites
US123731162025
Dynamic Read Retry Voltage Sequences in a Memory Subsystem
MICRON TECHNOLOGY, Inc.
0 cites
US123331602025
Memory Read Operation Using a Voltage Pattern Based on a Read Command Type
Micron Technology, Inc.
0 cites
US122549262025
Memory Device with Fast Write Mode to Mitigate Power Loss
Micron Technology, Inc.
0 cites
US122493782025
CELSRC Voltage Separation Between SLC and XLC for SLC Program Average ICC Reduction
Sandisk Technologies LLC
0 cites
US122486972025
Dynamic Read Level Trim Selection for Scan Operations of Memory Devices
Micron Technology, Inc.
0 cites
US122370152025
Adaptive Sensing Time for Memory Operations
MICRON TECHNOLOGY, Inc.
0 cites
US122370032025
Management of Dynamic Read Voltage Sequences in a Memory Subsystem
MICRON TECHNOLOGY, Inc.
0 cites
US122115562025
Independent Sensing Times
Micron Technology, Inc.
0 cites
US121977392025
Adaptive Bitline Voltage for Memory Operations
MICRON TECHNOLOGY, Inc.
0 cites
US121899612025
Charge Loss Mitigation Through Dynamic Programming Sequence
Micron Technology, Inc.
0 cites
US121701172024
3D NAND Memory with Built-in Capacitor
Micron Technology, Inc.
0 cites
US121546352024
Memory Programming Techniques to Reduce Power Consumption
Sanddisk Technologies LLC
0 cites
US121484802024
3D NAND Memory with Fast Corrective Read
Micron Technology, Inc.
0 cites
US121423262024
Adaptive Programming Delay Scheme in a Memory Sub-system
Micron Technology, Inc.
0 cites
US121068122024
Detecting a Memory Write Reliability Risk Without Using a Write Verify Operation
Micron Technology, Inc.
0 cites
US120790792024
Proximity Based Parity Data Management
Micron Technology, Inc.
0 cites
US120739052024
Adaptive Error Avoidance in the Memory Devices
Micron Technology, Inc.
0 cites
US120672552024
Error Detection for Programming Single Level Cells
Micron Technology, Inc.
0 cites
US120571672024
Padding in Flash Memory Blocks
Micron Technology, Inc.
0 cites
US120571572024
Low Power Mode with Read Sequence Adjustment
Sandisk Techn Ologies LLC
0 cites
US120272102024
Programming Delay Scheme for a Memory Sub-system Based on Memory Reliability
Micron Technology, Inc.
0 cites
US120140492024
Adaptive Sensing Time for Memory Operations
MICRON TECHNOLOGY, Inc.
0 cites
US119728012024
Program Voltage Dependent Program Source Levels
Sandisk Technologies, LLC
0 cites
US119728032024
Word Line Zone Dependent Pre-charge Voltage
Sandisk Technologies, LLC
0 cites
US119728092024
Selective Inhibit Bitline Voltage to Cells with Worse Program Disturb
Sandisk Technologies, LLC
0 cites
US119728142024
Verify Techniques for Current Reduction in a Memory Device
Sandisk Technologies, LLC
0 cites
US119721222024
Memory Read Operation Using a Voltage Pattern Based on a Read Command Type
Micron Technology, Inc.
0 cites
US118940812024
EP Cycling Dependent Asymmetric/symmetric VPASS Conversion in Non-volatile Memory Structures
SANDISK TECHNOLOGIES LLC
0 cites
US118876702024
Controlling Bit Line Pre-charge Voltage Separately for Multi-level Memory Cells and Single-level Memory Cells to Reduce Peak Current Consumption
Sandisk Technologies LLC
0 cites
US118758422024
Systems and Methods for Staggering Read Operation of Sub-blocks
SANDISK TECHNOLOGIES LLC
0 cites
US118372962023
Non-volatile Memory with Adjusted Bit Line Voltage During Verify
Sandisk Technologies LLC
0 cites
US117909922023
State Dependent VPVD Voltages for More Uniform Threshold Voltage Distributions in a Memory Device
Sandisk Technologies LLC
0 cites
US117587182023
Three Dimensional Memory Device Containing Truncated Channels and Method of Operating the Same with Different Erase Voltages for Different Bit Lines
SANDISK TECHNOLOGIES LLC
0 cites
US116994942023
Peak and Average ICC Reduction by Tier-based Sensing During Program Verify Operations of Non-volatile Memory Structures
Sandisk Technologies LLC
0 cites
US116640752023
Sub-block Programming Mode with Multi-tier Block
Sandisk Technologies LLC
0 cites
US116003432023
Efficient Read of NAND with Read Disturb Mitigation
Sandisk Technologies LLC
0 cites
US115876192023
Block Configuration for Memory Device with Separate Sub-blocks
Sandisk Technologies LLC
0 cites