8 Patents
- US125754672026Semiconductor Package Having Reduced Parasitic Inductance
ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
0 cites - US125688452026Chip Scale Semiconductor Package Having Back Side Metal Layer and Raised Front Side Pad and Method of Making the Same
ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
0 cites - US122611012025Semiconductor Package Having Wettable Lead Flanks and Tie Bars and Method of Making the Same
ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
0 cites - US121425482024Semiconductor Package Having Mold Locking Feature
ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
0 cites - US117216652023Wafer Level Chip Scale Semiconductor Package
ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
0 cites - US116996272023DMOS FET Chip Scale Package and Method of Making the Same
ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
0 cites - US116886712023Semiconductor Package Having a Lead Frame Including Die Paddles and Method of Making the Same
ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL, LP
0 cites - US115811952023Semiconductor Package Having Wettable Lead Flank and Method of Making the Same
ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
0 cites