Xavier F. Brun

5 Patents

• US126160132026

  Dielectric Bondable Chiplet for Package Architecture Including Reset via Simplification

  Intel Corporation

  0 cites
• US126160262026

  Permanent Layer for Bump Chip Attach

  Intel Corporation

  0 cites
• US125990502026

  Multi-level Die Coupled with a Substrate

  Intel Corporation

  0 cites
• US118044702023

  Wafer Level Passive Heat Spreader Interposer to Enable Improved Thermal Solution for Stacked Dies in Multi-chips Package and Warpage Control

  Intel Corporation

  0 cites
• US117054172023

  Backside Metallization (BSM) on Stacked Die Packages and External Silicon at Wafer Level, Singulated Die Level, or Stacked Dies Level

  Intel Corporation

  0 cites