Patents/Inventors

Willy Rachmady

Beaverton, ORUS75 patents

89 Patents

US125817172026
Frontside and Backside Epi Contact
Intel Corporation
0 cites
US125751842026
CMOS Architecture with Thermally Stable Silicide Gate Workfunction Metal
Intel Corporation
0 cites
US125503732026
Selective Removal of Channel Bodies in Stacked Gate-all-around (GAA) Device Structures
INTEL CORPORATION
0 cites
US125139582025
Nanowire Transistor Fabrication with Hardmask Layers
Sony Group Corporation
0 cites
US124330072025
Transistor Gate Trench Engineering to Decrease Capacitance and Resistance
Intel Corporation
0 cites
US123880112025
Top Gate Recessed Channel CMOS Thin Film Transistor and Methods of Fabrication
Intel Corporation
0 cites
US123693992025
Gate-to-gate Isolation for Stacked Transistor Architecture via Selective Dielectric Deposition Structure
INTEL CORPORATION
0 cites
US123639672025
Integration Methods to Fabricate Internal Spacers for Nanowire Devices
Sony Group Corporation
0 cites
US123426142025
Asymmetric Gate Structures and Contacts for Stacked Transistors
Intel Corporation
0 cites
US122888032025
Transistor with Isolation Below Source and Drain
Intel Corporation
0 cites
US122888072025
Amorphization and Regrowth of Source-drain Regions from the Bottom-side of a Semiconductor Assembly
Intel Corporation
0 cites
US122888132025
Gate-all-around Integrated Circuit Structures Having Insulator Fin on Insulator Substrate
Intel Corporation
0 cites
US122665702025
Self-aligned Interconnect Structures and Methods of Fabrication
Intel Corporation
0 cites
US122551372025
Sideways Vias in Isolation Areas to Contact Interior Layers in Stacked Devices
Intel Corporation
0 cites
US122242022025
Forming an Oxide Volume Within a Fin
Intel Corporation
0 cites
US121991422025
Neighboring Gate-all-around Integrated Circuit Structures Having Conductive Contact Stressor Between Epitaxial Source or Drain Regions
Intel Corporation
0 cites
US121836682024
Thin-film Transistors and MIM Capacitors in Exclusion Zones
Intel Corporation
0 cites
US121764082024
Localized Spacer for Nanowire Transistors and Methods of Fabrication
Intel Corporation
0 cites
USRE0502222024
Non-planar Gate All-around Device and Method of Fabrication Thereof
Sony Group Corporation
0 cites
US121488062024
Stacked Source-drain-gate Connection and Process for Forming Such
Intel Corporation
0 cites
US121426342024
Silicon and Silicon Germanium Nanowire Structures
Sony Group Corporation
0 cites
US121070852024
Interconnect Techniques for Electrically Connecting Source/drain Regions of Stacked Transistors
Intel Corporation
0 cites
US120877502024
Stacked-substrate FPGA Semiconductor Devices
Intel Corporation
0 cites
US120806052024
Backside Contacts for Semiconductor Devices
Intel Corporation
0 cites
US120683192024
High Performance Semiconductor Oxide Material Channel Regions for NMOS
Intel Corporation
0 cites
US120517232024
Pn-body-tied Field Effect Transistors
Intel Corporation
0 cites
US120466372024
Nanowire Transistor Fabrication with Hardmask Layers
Sony Group Corporation
0 cites
US120338962024
Isolation Wall Stressor Structures to Improve Channel Stress and Their Methods of Fabrication
Intel Corporation
0 cites
US120209292024
Epitaxial Layer with Substantially Parallel Sides
Intel Corporation
0 cites
US119964042024
Three-dimensional Integrated Circuits (3dics) Including Bottom Gate MOS Transistors with Monocrystalline Channel Material
Intel Corporation
0 cites
US119964082024
Leave-behind Protective Layer Having Secondary Purpose
Intel Corporation
0 cites
US119964112024
Stacked Forksheet Transistors
Intel Corporation
0 cites
US119964472024
Field Effect Transistors with Gate Electrode Self-aligned to Semiconductor Fin
Intel Corporation
0 cites
US119904762024
Semiconductor Nanowire Device Having (111)-plane Channel Sidewalls
Intel Corporation
0 cites
US119424162024
Sideways Vias in Isolation Areas to Contact Interior Layers in Stacked Devices
Intel Corporation
0 cites
US119358912024
Non-silicon N-type and P-type Stacked Transistors for Integrated Circuit Devices
Intel Corporation
0 cites
US119293202024
Top Gate Recessed Channel CMOS Thin Film Transistor in the Back End of Line and Methods of Fabrication
Intel Corporation
0 cites
US119294352024
Ferroelectric Gate Stack for Band-to-band Tunneling Reduction
Intel Corporation
0 cites
US119234102024
Transistor with Isolation Below Source and Drain
Intel Corporation
0 cites
US119234122024
Sub-fin Leakage Reduction for Template Strained Materials
Intel Corporation
0 cites
US119161182024
Stacked Source-drain-gate Connection and Process for Forming Such
Intel Corporation
0 cites
US118943722024
Stacked Trigate Transistors with Dielectric Isolation and Process for Forming Such
Intel Corporation
0 cites
US118944652024
Deep Gate-all-around Semiconductor Device Having Germanium or Group III-V Active Layer
Google LLC
0 cites
US118879882024
Thin Film Transistor Structures with Regrown Source and Drain
Intel Corporation
0 cites
US118698902024
Stacked Transistors with Contact Last
Intel Corporation
0 cites
US118698942024
Metallization Structures for Stacked Device Connectivity and Their Methods of Fabrication
Intel Corporation
0 cites
US118699392024
Integration Methods to Fabricate Internal Spacers for Nanowire Devices
Sony Group Corporation
0 cites
US118627022024
Gate-all-around Integrated Circuit Structures Having Insulator FIN on Insulator Substrate
Intel Corporation
0 cites
US118627152024
Vertical Tunneling Field-effect Transistors
Intel Corporation
0 cites
US118309332023
Gate-all-around Integrated Circuit Structures Having Depopulated Channel Structures Using Bottom-up Oxidation Approach
Intel Corporation
0 cites
US117989912023
Amorphization and Regrowth of Source-drain Regions from the Bottom-side of a Semiconductor Assembly
Intel Corporation
0 cites
US117842392023
Subfin Leakage Suppression Using Fixed Charge
Intel Corporation
0 cites
US117768982023
Sidewall Interconnect Metallization Structures for Integrated Circuit Devices
Intel Corporation
0 cites
US117770132023
Channel Formation for Three Dimensional Transistors
Intel Corporation
0 cites
US117641042023
Forming an Oxide Volume Within a Fin
Intel Corporation
0 cites
US117642632023
Gate-all-around Integrated Circuit Structures Having Depopulated Channel Structures Using Multiple Bottom-up Oxidation Approaches
Intel Corporation
0 cites
US117642752023
Indium-containing Fin of a Transistor Device with an Indium-rich Core
Intel Corporation
0 cites
US117642822023
Antiferroelectric Gate Dielectric Transistors and Their Methods of Fabrication
Intel Corporation
0 cites
US117569982023
Source-channel Junction for III-V Metal-oxide-semiconductor Field Effect Transistors (mosfets)
Intel Corporation
0 cites
US117423462023
Interconnect Techniques for Electrically Connecting Source/drain Regions of Stacked Transistors
Intel Corporation
0 cites
US117217352023
Thin Film Transistors Having U-shaped Features
Intel Corporation
0 cites
US116997042023
Monolithic Integration of a Thin Film Transistor Over a Complimentary Transistor
INTEL CORPORATION
0 cites
US116950812023
Channel Layer Formation for III-V Metal-oxide-semiconductor Field Effect Transistors (mosfets)
Intel Corporation
0 cites
US116769662023
Stacked Transistors Having Device Strata with Different Channel Widths
Intel Corporation
0 cites
US116770032023
Nanowire Transistor Fabrication with Hardmask Layers
Sony Group Corporation
0 cites
US116706822023
FINFET Transistor Having a Doped Sub Fin Structure to Reduce Channel to Substrate Leakage
Tahoe Research, Ltd.
0 cites
US116643732023
Isolation Walls for Vertically Stacked Transistor Structures
Intel Corporation
0 cites
US116643772023
Forksheet Transistor Architectures
Intel Corporation
0 cites
US116582082023
Thin Film Transistors for High Voltage Applications
Intel Corporation
0 cites
US116597222023
Thin-film-transistor Based Complementary Metal-oxide-semiconductor (CMOS) Circuit
Intel Corporation
0 cites
US116526062023
Advanced Encryption Standard Semiconductor Devices Fabricated on a Stacked-substrate
Intel Corporation
0 cites
US116463522023
Stacked Source-drain-gate Connection and Process for Forming Such
Intel Corporation
0 cites
US116409612023
III-V Source/drain in Top NMOS Transistors for Low Temperature Stacked Transistor Contacts
Intel Corporation
0 cites
US116317172023
3D Memory Array with Memory Cells Having a 3D Selector and a Storage Component
Intel Corporation
0 cites
US116317372023
Ingaas Epi Structure and Wet Etch Process for Enabling Iii-v GAA in Art Trench
Intel Corporation
0 cites
US116160562023
Vertical Diode in Stacked Transistor Architecture
Intel Corporation
0 cites
US116160572023
IC Including Back-end-of-line (BEOL) Transistors with Crystalline Channel Material
Intel Corporation
0 cites
US116160602023
Techniques for Forming Gate Structures for Transistors Arranged in a Stacked Configuration on a Single Fin Structure
Intel Corporation
0 cites
US116055652023
Three Dimensional Integrated Circuits with Stacked Transistors
Intel Corporation
0 cites
US116006962023
Sub-fin Leakage Reduction for Template Strained Materials
Intel Corporation
0 cites
US115945332023
Stacked Trigate Transistors with Dielectric Isolation Between First and Second Semiconductor Fins
Intel Corporation
0 cites
US115737982023
Stacked Transistors with Different Gate Lengths in Different Device Strata
Intel Corporation
0 cites
US115749102023
Device with Air-gaps to Reduce Coupling Capacitance and Process for Forming Such
Intel Corporation
0 cites
US115692332023
Techniques and Mechanisms for Operation of Stacked Transistors
Intel Corporation
0 cites
US115692382023
Vertical Memory Cells
Intel Corporation
0 cites
US115692432023
Stacked-substrate DRAM Semiconductor Devices
Intel Corporation
0 cites
US115631192023
Etchstop Regions in Fins of Semiconductor Devices
Intel Corporation
0 cites
US115576582023
Transistors with High Density Channel Semiconductor Over Dielectric Material
Intel Corporation
0 cites
US115521042023
Stacked Transistors with Dielectric Between Channels of Different Device Strata
Intel Corporation
0 cites