Patents/Inventors

Victor Moroz

Saratoga, CAUS16 patents

15 Patents

US125819332026
Power Routing for 2.5D or 3D Integrated Circuits Including a Buried Power Rail and Interposer with Power Delivery Network
Synopsys, Inc.
0 cites
US124531292025
Stacked Nanosheet Device for Process and Performance Optimization
Synopsys, Inc.
0 cites
US123681002025
Interconnects, Inductors, Transformers, and Power Architectures for Circuits
SYNOPSYS, Inc.
0 cites
US123004932025
Isolating Ion Implantation of Silicon Channels for Integrated Circuit Layout
Synopsys, Inc.
0 cites
US120865232024
Adaptive Row Patterns for Custom-tiled Placement Fabrics for Mixed Height Cell Libraries
Synopsys, Inc.
0 cites
US120806082024
Self-limiting Manufacturing Techniques to Prevent Electrical Shorts in a Complementary Field Effect Transistor (CFET)
Synopsys, Inc.
0 cites
US120418582024
Josephson Junction Structures
Synopsys, Inc.
0 cites
US119843842024
Power Routing for 2.5D or 3D Integrated Circuits Including a Buried Power Rail and Interposer with Power Delivery Network
Synopsys, Inc.
0 cites
US119375072024
Power Harvesting for Integrated Circuits
Synopsys, Inc.
0 cites
US119159842024
Forming a Wrap-around Contact to Connect a Source or Drain Epitaxial Growth of a Complimentary Field Effect Transistor (CFET) to a Buried Power Rail (BPR) of the CFET
Synopsys, Inc.
0 cites
US118940492024
CFET SRAM Cell Utilizing 8 Transistors
Synopsys, Inc.
0 cites
US118372802023
CFET Architecture for Balancing Logic Library and SRAM Bitcell
Synopsys, Inc.
0 cites
US117768162023
Fin Patterning to Reduce Fin Collapse and Transistor Leakage
Synopsys, Inc.
0 cites
US117422472023
Epitaxial Growth of Source and Drain Materials in a Complementary Field Effect Transistor (CFET)
Synopsys, Inc.
0 cites
US117106342023
Fabrication Technique for Forming Ultra-high Density Integrated Circuit Components
Synopsys, Inc.
0 cites