Patents/Inventors

Vasanth Ranganathan

El Dorado Hills, CAUS80 patents

78 Patents

US126137392026
Hard Partitioning via Intra-soc Composition
Intel Corporation
0 cites
US125855902026
Broadcast Asynchronous Loads to Shared Local Memory
Intel Corporation
0 cites
US125790722026
Graphics Processor Register File Including a Low Energy Portion and a High Capacity Portion
Intel Corporation
0 cites
US125729972026
Graphics Processing Unit Processing and Caching Improvements
Intel Corporation
0 cites
US125723922026
Flexible Partitioning of GPU Resources
Intel Corporation
0 cites
US125612762026
Systems and Methods for Updating Memory Side Caches in a Multi-gpu Configuration
INTEL CORPORATION
0 cites
US125546742026
Multi-tile Memory Management
Intel Corporation
0 cites
US125419082026
Apparatus and Method for Throttling a Ray Tracing Pipeline
Intel Corporation
0 cites
US125049892025
Load Store Bank Aware Thread Scheduling Techniques
Intel Corporation
0 cites
US124995032025
Multi-render Partitioning
Intel Corporation
0 cites
US124939222025
Graphics Processing Unit Processing and Caching Improvements
Intel Corporation
0 cites
US124623282025
Coordination and Increased Utilization of Graphics Processors During Inference
Intel Corporation
0 cites
US123867792025
Dynamic Memory Reconfiguration
Intel Corporation
0 cites
US123616002025
Systolic Arithmetic on Sparse Data
Intel Corporation
0 cites
US123467982025
Dynamic Precision for Neural Network Compute Operations
INTEL CORPORATION
0 cites
US123067712025
Efficient Data Sharing for Graphics Data Processing Operations
INTEL CORPORATION
0 cites
US122997662025
Providing Native Support for Generic Pointers in a Graphics Processing Unit
Intel Corporation
0 cites
US122934312025
Sparse Optimizations for a Matrix Accelerator Architecture
Intel Corporation
0 cites
US122424142025
Data Initialization Techniques
INTEL CORPORATION
0 cites
US122364982025
Generation and Storage of Compressed Z-planes in Graphics Processing
INTEL CORPORATION
0 cites
US122298712025
Motion Biased Foveated Renderer
Intel Corporation
0 cites
US122170532025
Instructions and Logic to Perform Floating Point and Integer Operations for Machine Learning
Intel Corporation
0 cites
US122109002025
Efficient Thread Group Scheduling
INTEL CORPORATION
0 cites
US122104772025
Systems and Methods for Improving Cache Efficiency and Utilization
Intel Corporation
0 cites
US122044872025
Graphics Processor Data Access and Sharing
INTEL CORPORATION
0 cites
US121982222025
Architecture for Block Sparse Operations on a Systolic Array
Intel Corporation
0 cites
US121904412025
Fragment Compression for Coarse Pixel Shading
Intel Corporation
0 cites
US121901182025
Data Locality Enhancement for Graphics Processing Units
INTEL CORPORATION
0 cites
US121820352024
Systems and Methods for Cache Optimization
Intel Corporation
0 cites
US121820622024
Multi-tile Memory Management
Intel Corporation
0 cites
US121820232024
Opportunistic Late Depth Testing to Prevent Stalling for Overlapping Cache Lines
Intel Corporation
0 cites
US121649522024
Barrier State Save and Restore for Preemption in a Graphics Environment
INTEL CORPORATION
0 cites
US121535412024
Cache Structure and Utilization
INTEL CORPORATION
0 cites
US121473022024
Systems and Methods for Error Detection and Control for Embedded Memory and Compute Elements
Intel Corporation
0 cites
US121410942024
Systolic Disaggregation Within a Matrix Accelerator Architecture
Intel Corporation
0 cites
US121415782024
Instructions and Logic to Perform Floating Point and Integer Operations for Machine Learning
Intel Corporation
0 cites
US121243832024
Systems and Methods for Cache Optimization
Intel Corporation
0 cites
US121248522024
Instruction Prefetch Based on Thread Dispatch Commands
Intel Corporation
0 cites
US120994612024
Multi-tile Memory Management
INTEL CORPORATION
0 cites
US120940482024
Multi-tile Graphics Processor Rendering
INTEL CORPORATION
0 cites
US120932102024
Compression Techniques
INTEL CORPORATION
0 cites
US120669752024
Cache Structure and Utilization
INTEL CORPORATION
0 cites
US120560592024
Systems and Methods for Cache Optimization
Intel Corporation
0 cites
US120456582024
Stack Access Throttling for Synchronous Ray Tracing
Intel Corporation
0 cites
US120393312024
Instructions and Logic to Perform Floating Point and Integer Operations for Machine Learning
Intel Corporation
0 cites
US120324962024
Efficient Data Sharing for Graphics Data Processing Operations
INTEL CORPORATION
0 cites
US120203702024
Enhancing Hierarchical Depth Buffer Culling Efficiency via Mask Accumulation
Intel Corporation
0 cites
US120138082024
Multi-tile Architecture for Graphics Operations
INTEL CORPORATION
0 cites
US120012092024
Barriers and Synchronization for Machine Learning at Autonomous Machines
Intel Corporation
0 cites
US119950292024
Multi-tile Memory Management for Detecting Cross Tile Access Providing Multi-tile Inference Scaling and Providing Page Migration
Intel Corporation
0 cites
US119611792024
Fragment Compression for Coarse Pixel Shading
Intel Corporation
0 cites
US119540622024
Dynamic Memory Reconfiguration
Intel Corporation
0 cites
US119343422024
Assistance for Hardware Prefetch in Cache Access
INTEL CORPORATION
0 cites
US119153572024
Apparatus and Method for Throttling a Ray Tracing Pipeline
Intel Corporation
0 cites
US118929502024
Data Prefetching for Graphics Data Processing
INTEL CORPORATION
0 cites
US118682642024
Sector Cache for Compression
Intel Corporation
0 cites
US118617612024
Graphics Processing Unit Processing and Caching Improvements
Intel Corporation
0 cites
US118424232023
Dot Product Operations on Sparse Matrix Elements
Intel Corporation
0 cites
US118099052023
Local Memory Sharing Between Kernels
Intel Corporation
0 cites
US117978372023
Dynamic Distributed Training of Machine Learning Models
Intel Corporation
0 cites
US117626622023
Instruction Prefetch Based on Thread Dispatch Commands
Intel Corporation
0 cites
US117555012023
Efficient Data Sharing for Graphics Data Processing Operations
INTEL CORPORATION
0 cites
US117486062023
Dynamic Precision for Neural Network Compute Operations
INTEL CORPORATION
0 cites
US117488412023
Coordination and Increased Utilization of Graphics Processors During Inference
Intel Corporation
0 cites
US117481062023
Data Operations and Finite State Machine for Machine Learning via Bypass of Computational Tasks Based on Frequently-used Data Values
INTEL CORPORATION
0 cites
US117268262023
Dynamic Load Balancing of Compute Assets Among Different Compute Contexts
Intel Corporation
0 cites
US117267932023
Data Locality Enhancement for Graphics Processing Units
INTEL CORPORATION
0 cites
US117203552023
Instructions and Logic to Perform Floating Point and Integer Operations for Machine Learning
Intel Corporation
0 cites
US116762392023
Sparse Optimizations for a Matrix Accelerator Architecture
Intel Corporation
0 cites
US116700442023
Fragment Compression for Coarse Pixel Shading
Intel Corporation
0 cites
US116637462023
Systolic Arithmetic on Sparse Data
Intel Corporation
0 cites
US116202562023
Systems and Methods for Improving Cache Efficiency and Utilization
Intel Corporation
0 cites
US116155842023
Hierarchical Depth Buffer Back Annotation
Intel Corporation
0 cites
US116155852023
Enhancing Hierarchical Depth Buffer Culling Efficiency via Mask Accumulation
Intel Corporation
0 cites
US115932602023
Memory Compression Hashing Mechanism
Intel Corporation
0 cites
US115928172023
Storage Management for Machine Learning at Autonomous Machines
INTEL CORPORATION
0 cites
US115932692023
Sector Cache for Compression
Intel Corporation
0 cites
US115865482023
Sector Cache for Compression
Intel Corporation
0 cites