Patents/Inventors

Varghese George

Miramar, FLUS77 patents

71 Patents

US125943232026
Methods of Reducing Neuroinflammation
Immunitybio, Inc.
0 cites
US125612762026
Systems and Methods for Updating Memory Side Caches in a Multi-gpu Configuration
INTEL CORPORATION
0 cites
US125612772026
Memory Controller Management Techniques for Managing Data Transfer for Memory Access Operations
INTEL CORPORATION
0 cites
US125544892026
Supporting 8-bit Floating Point Format Operands in a Computing Architecture
INTEL CORPORATION
0 cites
US125546742026
Multi-tile Memory Management
Intel Corporation
0 cites
US124301282025
Sharing Register File Usage Between Fused Processing Resources
Intel Corporation
0 cites
US124057872025
Utilizing Structured Sparsity in Systolic Arrays
INTEL CORPORATION
0 cites
US123981892025
Methods of Activating Regulatory T Cells
HCW Biologics, Inc.
0 cites
US123996852025
Systolic Array Having Support for Output Sparsity
Intel Corporation
0 cites
US123867792025
Dynamic Memory Reconfiguration
Intel Corporation
0 cites
US123739122025
Prefetch Status Notification for Memory Prefetching
INTEL CORPORATION
0 cites
US123466942025
Register File for Systolic Array
Intel Corporation
0 cites
US123213102025
Implicit Fence for Write Messages
Intel Corporation
0 cites
US123067712025
Efficient Data Sharing for Graphics Data Processing Operations
INTEL CORPORATION
0 cites
US122934312025
Sparse Optimizations for a Matrix Accelerator Architecture
Intel Corporation
0 cites
US122545262025
On Chip Dense Memory for Temporal Buffering
Intel Corporation
0 cites
US122424142025
Data Initialization Techniques
INTEL CORPORATION
0 cites
US122428462025
Supporting 8-bit Floating Point Format Operands in a Computing Architecture
INTEL CORPORATION
0 cites
US122295812025
Virtualization and Multi-tenancy Support in Graphics Processors
Intel Corporation
0 cites
US122298672025
Graphics Architecture Including a Neural Network Pipeline
Intel Corporation
0 cites
US122233532025
Systems and Methods for Synchronization of Multi-thread Lanes
INTEL CORPORATION
0 cites
US122104772025
Systems and Methods for Improving Cache Efficiency and Utilization
Intel Corporation
0 cites
US122044872025
Graphics Processor Data Access and Sharing
INTEL CORPORATION
0 cites
US121982222025
Architecture for Block Sparse Operations on a Systolic Array
Intel Corporation
0 cites
US121820352024
Systems and Methods for Cache Optimization
Intel Corporation
0 cites
US121820622024
Multi-tile Memory Management
Intel Corporation
0 cites
US121747832024
Systolic Array of Arbitrary Physical and Logical Depth
Intel Corporation
0 cites
US121535412024
Cache Structure and Utilization
INTEL CORPORATION
0 cites
US121410942024
Systolic Disaggregation Within a Matrix Accelerator Architecture
Intel Corporation
0 cites
US121418902024
Enabling Product Skus Based on Chiplet Configurations
Intel Corporation
0 cites
US121243832024
Systems and Methods for Cache Optimization
Intel Corporation
0 cites
US121179622024
Scalar Core Integration
INTEL CORPORATION
0 cites
US121123982024
Disaggregation of System-on-chip (SOC) Architecture
Intel Corporation
0 cites
US120994612024
Multi-tile Memory Management
INTEL CORPORATION
0 cites
US120932102024
Compression Techniques
INTEL CORPORATION
0 cites
US120791552024
Graphics Processor Operation Scheduling for Deterministic Latency
Intel Corporation
0 cites
US120669752024
Cache Structure and Utilization
INTEL CORPORATION
0 cites
US120560592024
Systems and Methods for Cache Optimization
Intel Corporation
0 cites
US120567892024
Disaggregation of System-on-chip (SOC) Architecture
Intel Corporation
0 cites
US120390012024
Scalable Sparse Matrix Multiply Acceleration Using Systolic Arrays with Feedback Inputs
Intel Corporation
0 cites
US120324962024
Efficient Data Sharing for Graphics Data Processing Operations
INTEL CORPORATION
0 cites
US120245452024
Methods of Treating Aging-related Disorders
HCW Biologics, Inc.
0 cites
US120138082024
Multi-tile Architecture for Graphics Operations
INTEL CORPORATION
0 cites
US120079352024
Graphics Processors and Graphics Processing Units Having Dot Product Accumulate Instruction for Hybrid Floating Point Format
Intel Corporation
0 cites
US119950292024
Multi-tile Memory Management for Detecting Cross Tile Access Providing Multi-tile Inference Scaling and Providing Page Migration
Intel Corporation
0 cites
US119778852024
Utilizing Structured Sparsity in Systolic Arrays
INTEL CORPORATION
0 cites
US119540622024
Dynamic Memory Reconfiguration
Intel Corporation
0 cites
US119540632024
Graphics Processors and Graphics Processing Units Having Dot Product Accumulate Instruction for Hybrid Floating Point Format
Intel Corporation
0 cites
US119343422024
Assistance for Hardware Prefetch in Cache Access
INTEL CORPORATION
0 cites
US118996142024
Instruction Based Control of Memory Attributes
Intel Corporation
0 cites
US119001142024
Systems and Methods to Skip Inconsequential Matrix Operations
Intel Corporation
0 cites
US118691132024
Systems and Methods for Exploiting Queues and Transitional Storage for Improved Low-latency High-bandwidth On-die Data Retrieval
Intel Corporation
0 cites
US118617592024
Memory Prefetching in Multiple GPU Environment
INTEL CORPORATION
0 cites
US118424232023
Dot Product Operations on Sparse Matrix Elements
Intel Corporation
0 cites
US118165002023
Systems and Methods for Synchronization of Multi-thread Lanes
Intel Corporation
0 cites
US118099052023
Local Memory Sharing Between Kernels
Intel Corporation
0 cites
US117861582023
Devices and Methods for Sensing Bladder Fullness
Incube Labs, LLC
0 cites
US117628042023
Scalar Core Integration
INTEL CORPORATION
0 cites
US117634162023
Disaggregation of System-on-chip (SOC) Architecture
Intel Corporation
0 cites
US117555012023
Efficient Data Sharing for Graphics Data Processing Operations
INTEL CORPORATION
0 cites
US117561502023
Disaggregation of System-on-chip (SOC) Architecture
Intel Corporation
0 cites
US117481302023
Virtualization and Multi-tenancy Support in Graphics Processors
INTEL CORPORATION
0 cites
US117097932023
Graphics Processors and Graphics Processing Units Having Dot Product Accumulate Instruction for Hybrid Floating Point Format
Intel Corporation
0 cites
US116762392023
Sparse Optimizations for a Matrix Accelerator Architecture
Intel Corporation
0 cites
US116763222023
Graphics Architecture Including a Neural Network Pipeline
Intel Corporation
0 cites
US116693292023
Instructions and Logic for Vector Multiply Add with Zero Skipping
Intel Corporation
0 cites
US116402972023
Instruction and Logic for Systolic Dot Product with Accumulate
Intel Corporation
0 cites
US116361742023
Scalable Sparse Matrix Multiply Acceleration Using Systolic Arrays with Feedback Inputs
Intel Corporation
0 cites
US116202562023
Systems and Methods for Improving Cache Efficiency and Utilization
Intel Corporation
0 cites
US115618282023
Graphics Systems and Methods for Accelerating Synchronization Using Fine Grain Dependency Check and Scheduling Optimizations Based on Available Shared Memory Space
Intel Corporation
0 cites
US115570852023
Neural Network Processing for Multi-object 3D Modeling
Intel Corporation
0 cites