Patents/Inventors

Travis W. Lajoie

Forest Grove, ORUS45 patents

33 Patents

US126220422026
Multi-layered or Graded Gate Dielectric in Thin Film Transistor (TFT) Structures
INTEL CORPORATION
0 cites
US126219792026
Multi-tier Memory Structure with Graded Characteristics
INTEL CORPORATION
0 cites
US126105822026
Multi-layered Source and Drain Contacts for a Thin Film Transistor (TFT) Structure
Intel Corporation
0 cites
US125990322026
Bilayer Memory Stacking with Lines Shared Between Bottom and Top Memory Layers
Intel Corporation
0 cites
US125882412026
Asymmetric Source and Drain Contacts for a Thin Film Transistor (TFT) Structure
INTEL CORPORATION
0 cites
US125640352026
Airgaps Used in Backend Memory Structures
Intel Corporation
0 cites
US125124092025
Hybrid Etch Stop Layers
INTEL CORPORATION
0 cites
US125139702025
Integrated Circuits with Tungsten Interconnect Liners
Intel Corporation
0 cites
US124904602025
Dielectric Sidewall Features for Tuning Thin Film Transistor (TFT) Parasitics
Intel Corporation
0 cites
US124761832025
Punch-through Interconnect Feature to Couple Upper Electrodes of Capacitors of Multi-level Memory Arrays
Intel Corporation
0 cites
US124446782025
Spacer-based Self-aligned Interconnect Features
Intel Corporation
0 cites
US124462082025
Multilevel Wordline Assembly for Embedded DRAM
Intel Corporation
0 cites
US124262472025
Capacitor Connections in Dielectric Layers
Intel Corporation
0 cites
US123961552025
Backend Memory with Air Gaps in Upper Metal Layers
Intel Corporation
0 cites
US123763422025
Passivation Layers for Thin Film Transistors
Intel Corporation
0 cites
US123100012025
Decoupling Capacitors and Methods of Fabrication
Intel Corporation
0 cites
US122389132025
Two Transistor Memory Cell Using Stacked Thin-film Transistors
Intel Corporation
0 cites
US121761472024
Three-dimensional Capacitors with Double Metal Electrodes
Intel Corporation
0 cites
US121487342024
Transistors, Memory Cells, and Arrangements Thereof
Intel Corporation
0 cites
US121502972024
Thin Film Transistors Having a Backside Channel Contact for High Density Memory
Intel Corporation
0 cites
US120806432024
Integrated Circuit Structures Having Differentiated Interconnect Lines in a Same Dielectric Layer
Intel Corporation
0 cites
US120807812024
Fabrication of Thin Film Fin Transistor Structure
Intel Corporation
0 cites
US119918732024
Capacitor Separations in Dielectric Layers
Intel Corporation
0 cites
US119555602024
Passivation Layers for Thin Film Transistors and Methods of Fabrication
Intel Corporation
0 cites
US119504072024
Memory Architecture with Shared Bitline at Back-end-of-line
Intel Corporation
0 cites
US119294152024
Thin Film Transistors with Offset Source and Drain Structures and Process for Forming Such
Intel Corporation
0 cites
US118324382023
Capacitor Connections in Dielectric Layers
Intel Corporation
0 cites
US117587112023
Thin-film Transistor Embedded Dynamic Random-access Memory with Shallow Bitline
Intel Corporation
0 cites
US116839292023
Method for Making Memory Cells Based on Thin-film Transistors
Intel Corporation
0 cites
US116520472023
Intermediate Separation Layers at the Back-end-of-line
Intel Corporation
0 cites
US116108942023
Capacitor Separations in Dielectric Layers
Intel Corporation
0 cites
US115749102023
Device with Air-gaps to Reduce Coupling Capacitance and Process for Forming Such
Intel Corporation
0 cites
US115631072023
Method of Contact Patterning of Thin Film Transistors for Embedded DRAM Using a Multi-layer Hardmask
Intel Corporation
0 cites