Patents/Inventors

Timothy D. Anderson

University Park, TXUS33 patents

31 Patents

US125789632026
Implied Fence on Stream Open
TEXAS INSTRUMENTS INCORPORATED
0 cites
US124815032025
Vector Maximum and Minimum with Indexing
TEXAS INSTRUMENTS INCORPORATED
0 cites
US124234812025
Secure Master and Secure Guest Endpoint Security Firewall
TEXAS INSTRUMENTS INCORPORATED
0 cites
US123798502025
Memory Controller with Command Reordering
TEXAS INSTRUMENTS INCORPORATED
0 cites
US123732422025
Entering Protected Pipeline Mode Without Annulling Pending Instructions
Texas Instruments Incorporated
0 cites
US123671502025
Streaming Engine with Early and Late Address and Loop Count Registers to Track Architectural State
Texas Instruments Incorporated
0 cites
US123332842025
Nested Loop Control
Texas Instruments Incorporated
0 cites
US123217502025
Entering Protected Pipeline Mode with Clearing
Texas Instruments Incorporated
0 cites
US123114742025
Field Girth Welding Technology for High Manganese Steel Slurry Pipelines
POSCO
0 cites
US123141872025
Software-hardware Memory Management Modes
Texas Instruments Incorporated
0 cites
US123072512025
Vector Reverse
TEXAS INSTRUMENTS INCORPORATED
0 cites
US122994462025
Streaming Engine with Stream Metadata Saving for Context Switching
Texas Instruments Incorporated
0 cites
US122602192025
Multiple Instruction Set Architectures on a Processing Device
Texas Instruments Incorporated
0 cites
US122233272025
Cpus with Capture Queues to Save and Restore Intermediate Results and Out-of-order Results
Texas Instruments Incorporated
0 cites
US121979172025
Exit History Based Branch Prediction
Texas Instruments Incorporated
0 cites
US121752442024
Nested Loop Control
Texas Instruments Incorporated
0 cites
US120994002024
Streaming Engine with Deferred Exception Reporting
TEXAS INSTRUMENTS INCORPORATED
0 cites
US120728122024
Highly Integrated Scalable, Flexible DSP Megamodule Architecture
Texas Instruments Incorporated
0 cites
US120728242024
Multicore Bus Architecture with Non-blocking High Performance Transaction Credit System
Texas Instruments Incorporated
0 cites
US120673962024
Variable Latency Instructions
Texas Instruments Incorporated
0 cites
US120329612024
Vector Maximum and Minimum with Indexing
Texas Instruments Incorporated
0 cites
US119722362024
Nested Loop Control
Texas Instruments Incorporated
0 cites
US119001122024
Vector Reverse
Texas Instruments Incorporated
0 cites
US118532252023
Software-hardware Memory Management Modes
Texas Instruments Incorporated
0 cites
US118164852023
Nested Loop Control
Texas Instruments Incorporated
0 cites
US117897422023
Pipeline Protection for Cpus with Save and Restore of Intermediate Results
Texas Instruments Incorporated
0 cites
US117827182023
Implied Fence on Stream Open
Texas Instruments Incorporated
0 cites
US117097782023
Streaming Engine with Early and Late Address and Loop Count Registers to Track Architectural State
Texas Instmments Incorporated
0 cites
US116936612023
Mechanism for Interrupting and Resuming Execution on an Unprotected Pipeline Processor
Texas Instruments Incorporated
0 cites
US116149402023
Vector Maximum and Minimum with Indexing
Texas Instruments Incorporated
0 cites
US115738472023
Streaming Engine with Deferred Exception Reporting
Texas Instruments Incorporated
0 cites