Theodore E. Fong

4 Patents

• US125820122026

  Method of Forming Semiconductor Device Using High Stress Cleave Plane

  Silicon Genesis Corporation

  0 cites
• US121763262024

  Method of Forming Semiconductor Device Using High Stress Cleave Plane

  Silicon Genesis Corporation

  0 cites
• US119013512024

  Three Dimensional Integrated Circuit with Lateral Connection Layer

  Silicon Genesis Corporation

  0 cites
• US116263922023

  Method of Forming Semiconductor Device Using Range Compensating Material

  Silicon Genesis Corporation

  0 cites