Patents/Inventors

Supratim Pal

Folsom, CAUS29 patents

26 Patents

US125790122026
Forward Progress Guarantee Using Single-level Synchronization at Individual Thread Granularity
INTEL CORPORATION
0 cites
US125544892026
Supporting 8-bit Floating Point Format Operands in a Computing Architecture
INTEL CORPORATION
0 cites
US124057872025
Utilizing Structured Sparsity in Systolic Arrays
INTEL CORPORATION
0 cites
US123996852025
Systolic Array Having Support for Output Sparsity
Intel Corporation
0 cites
US123866172025
Gathering Payload from Arbitrary Registers for Send Messages in a Graphics Environment
INTEL CORPORATION
0 cites
US123752622025
Fused Instruction to Accelerate Performance of Secure Hash Algorithm 2 (SHA-2) Workloads in a Graphics Environment
INTEL CORPORATION
0 cites
US123466942025
Register File for Systolic Array
Intel Corporation
0 cites
US122428462025
Supporting 8-bit Floating Point Format Operands in a Computing Architecture
INTEL CORPORATION
0 cites
US122362382025
Large Integer Multiplication Enhancements for Graphics Environment
INTEL CORPORATION
0 cites
US122109052025
Multiple Register Allocation Sizes for Threads
INTEL CORPORATION
0 cites
US121895712025
Dual Pipeline Parallel Systolic Array
Intel Corporation
0 cites
US121901582025
Using Sparsity Metadata to Reduce Systolic Array Power Consumption
Intel Corporation
0 cites
US121747832024
Systolic Array of Arbitrary Physical and Logical Depth
Intel Corporation
0 cites
US120932132024
Computing Efficient Cross Channel Operations in Parallel Computing Machines Using Systolic Arrays
INTEL CORPORATION
0 cites
US120390012024
Scalable Sparse Matrix Multiply Acceleration Using Systolic Arrays with Feedback Inputs
Intel Corporation
0 cites
US120079352024
Graphics Processors and Graphics Processing Units Having Dot Product Accumulate Instruction for Hybrid Floating Point Format
Intel Corporation
0 cites
US119778852024
Utilizing Structured Sparsity in Systolic Arrays
INTEL CORPORATION
0 cites
US119540632024
Graphics Processors and Graphics Processing Units Having Dot Product Accumulate Instruction for Hybrid Floating Point Format
Intel Corporation
0 cites
US119005022024
Compiler Assisted Register File Write Reduction
Intel Corporation
0 cites
US117097932023
Graphics Processors and Graphics Processing Units Having Dot Product Accumulate Instruction for Hybrid Floating Point Format
Intel Corporation
0 cites
US116693292023
Instructions and Logic for Vector Multiply Add with Zero Skipping
Intel Corporation
0 cites
US116694902023
Computing Efficient Cross Channel Operations in Parallel Computing Machines Using Systolic Arrays
INTEL CORPORATION
0 cites
US116402972023
Instruction and Logic for Systolic Dot Product with Accumulate
Intel Corporation
0 cites
US116361742023
Scalable Sparse Matrix Multiply Acceleration Using Systolic Arrays with Feedback Inputs
Intel Corporation
0 cites
US115930692023
Use of a Single Instruction Set Architecture (ISA) Instruction for Vector Normalization
Intel Corporation
0 cites
US115798782023
Register Sharing Mechanism to Equally Allocate Disabled Thread Registers to Active Threads
Intel Corporation
0 cites