Patents/Inventors

Subramaniam Maiyuran

Gold River, CAUS96 patents

97 Patents

US125797262026
Hierarchical Tiling Mechanism
INTEL CORPORATION
0 cites
US125729972026
Graphics Processing Unit Processing and Caching Improvements
Intel Corporation
0 cites
US125612762026
Systems and Methods for Updating Memory Side Caches in a Multi-gpu Configuration
INTEL CORPORATION
0 cites
US125612772026
Memory Controller Management Techniques for Managing Data Transfer for Memory Access Operations
INTEL CORPORATION
0 cites
US125544892026
Supporting 8-bit Floating Point Format Operands in a Computing Architecture
INTEL CORPORATION
0 cites
US125546742026
Multi-tile Memory Management
Intel Corporation
0 cites
US125111212025
Native Support for Execution of Get Exponent, Get Mantisssa, and Scale Instructions Within a Graphics Processing Unit via Reuse of Fused Multiply-add Execution Unit Hardware Logic
Intel Corporation
0 cites
US124939222025
Graphics Processing Unit Processing and Caching Improvements
Intel Corporation
0 cites
US124878242025
Immediate Offset of Load Store and Atomic Instructions
Intel Corporation
0 cites
US124508142025
Dynamic Tile Sequencing in Graphic Processing
INTEL CORPORATION
0 cites
US124367272025
Regional Adjustment of Render Rate
Intel Corporation
0 cites
US124301282025
Sharing Register File Usage Between Fused Processing Resources
Intel Corporation
0 cites
US124057872025
Utilizing Structured Sparsity in Systolic Arrays
INTEL CORPORATION
0 cites
US123996852025
Systolic Array Having Support for Output Sparsity
Intel Corporation
0 cites
US123997342025
Engine to Enable High Speed Context Switching via On-die Storage
INTEL CORPORATION
0 cites
US123866172025
Gathering Payload from Arbitrary Registers for Send Messages in a Graphics Environment
INTEL CORPORATION
0 cites
US123867792025
Dynamic Memory Reconfiguration
Intel Corporation
0 cites
US123739122025
Prefetch Status Notification for Memory Prefetching
INTEL CORPORATION
0 cites
US123616002025
Systolic Arithmetic on Sparse Data
Intel Corporation
0 cites
US123466942025
Register File for Systolic Array
Intel Corporation
0 cites
US123333062025
High Performance Constant Cache and Constant Access Mechanisms
Intel Corporation
0 cites
US122934312025
Sparse Optimizations for a Matrix Accelerator Architecture
Intel Corporation
0 cites
US122934622025
Tile Sequencing Mechanism
Intel Corporation
0 cites
US122545262025
On Chip Dense Memory for Temporal Buffering
Intel Corporation
0 cites
US122424142025
Data Initialization Techniques
INTEL CORPORATION
0 cites
US122428462025
Supporting 8-bit Floating Point Format Operands in a Computing Architecture
INTEL CORPORATION
0 cites
US122295812025
Virtualization and Multi-tenancy Support in Graphics Processors
Intel Corporation
0 cites
US122233532025
Systems and Methods for Synchronization of Multi-thread Lanes
INTEL CORPORATION
0 cites
US122104772025
Systems and Methods for Improving Cache Efficiency and Utilization
Intel Corporation
0 cites
US122109052025
Multiple Register Allocation Sizes for Threads
INTEL CORPORATION
0 cites
US122044872025
Graphics Processor Data Access and Sharing
INTEL CORPORATION
0 cites
US121982212025
Compute Optimization Mechanism for Deep Neural Networks
Intel Corporation
0 cites
US121982222025
Architecture for Block Sparse Operations on a Systolic Array
Intel Corporation
0 cites
US121901182025
Data Locality Enhancement for Graphics Processing Units
INTEL CORPORATION
0 cites
US121904062025
Pointer De-referencing Technologies
Intel Corporation
0 cites
US121820352024
Systems and Methods for Cache Optimization
Intel Corporation
0 cites
US121820622024
Multi-tile Memory Management
Intel Corporation
0 cites
US121747832024
Systolic Array of Arbitrary Physical and Logical Depth
Intel Corporation
0 cites
US121644302024
Instruction Prefetch Mechanism
INTEL CORPORATION
0 cites
US121648842024
Tanh and Sigmoid Function Execution
Intel Corporation
0 cites
US121535412024
Cache Structure and Utilization
INTEL CORPORATION
0 cites
US121473022024
Systems and Methods for Error Detection and Control for Embedded Memory and Compute Elements
Intel Corporation
0 cites
US121410942024
Systolic Disaggregation Within a Matrix Accelerator Architecture
Intel Corporation
0 cites
US121243832024
Systems and Methods for Cache Optimization
Intel Corporation
0 cites
US121179622024
Scalar Core Integration
INTEL CORPORATION
0 cites
US120994612024
Multi-tile Memory Management
INTEL CORPORATION
0 cites
US121001032024
Converting Barycentric Planes to Attribute Planes
Intel Corporation
0 cites
US120932102024
Compression Techniques
INTEL CORPORATION
0 cites
US120932132024
Computing Efficient Cross Channel Operations in Parallel Computing Machines Using Systolic Arrays
INTEL CORPORATION
0 cites
US120669752024
Cache Structure and Utilization
INTEL CORPORATION
0 cites
US120673942024
Native Support for Execution of Get Exponent, Get Mantisssa, and Scale Instructions Within a Graphics Processing Unit via Reuse of Fused Multiply-add Execution Unit Hardware Logic
Intel Corporation
0 cites
US120618312024
Regional Adjustment of Render Rate
Intel Corporation
0 cites
US120560592024
Systems and Methods for Cache Optimization
Intel Corporation
0 cites
US120390012024
Scalable Sparse Matrix Multiply Acceleration Using Systolic Arrays with Feedback Inputs
Intel Corporation
0 cites
US120079352024
Graphics Processors and Graphics Processing Units Having Dot Product Accumulate Instruction for Hybrid Floating Point Format
Intel Corporation
0 cites
US120080672024
Sparse Matrix Multiplication Acceleration Mechanism
Intel Corporation
0 cites
US119950292024
Multi-tile Memory Management for Detecting Cross Tile Access Providing Multi-tile Inference Scaling and Providing Page Migration
Intel Corporation
0 cites
US119778852024
Utilizing Structured Sparsity in Systolic Arrays
INTEL CORPORATION
0 cites
US119540622024
Dynamic Memory Reconfiguration
Intel Corporation
0 cites
US119540632024
Graphics Processors and Graphics Processing Units Having Dot Product Accumulate Instruction for Hybrid Floating Point Format
Intel Corporation
0 cites
US119343422024
Assistance for Hardware Prefetch in Cache Access
INTEL CORPORATION
0 cites
US119347972024
Mechanism to Perform Single Precision Floating Point Extended Math Operations
Intel Corporation
0 cites
US119225352024
Compute Optimization Mechanism for Deep Neural Networks
Intel Corporation
0 cites
US119001142024
Systems and Methods to Skip Inconsequential Matrix Operations
Intel Corporation
0 cites
US119005022024
Compiler Assisted Register File Write Reduction
Intel Corporation
0 cites
US119005392024
Tile Sequencing Mechanism
Intel Corporation
0 cites
US118929502024
Data Prefetching for Graphics Data Processing
INTEL CORPORATION
0 cites
US118691132024
Systems and Methods for Exploiting Queues and Transitional Storage for Improved Low-latency High-bandwidth On-die Data Retrieval
Intel Corporation
0 cites
US118617592024
Memory Prefetching in Multiple GPU Environment
INTEL CORPORATION
0 cites
US118617612024
Graphics Processing Unit Processing and Caching Improvements
Intel Corporation
0 cites
US118424232023
Dot Product Operations on Sparse Matrix Elements
Intel Corporation
0 cites
US118163842023
Regional Adjustment of Render Rate
Intel Corporation
0 cites
US118165002023
Systems and Methods for Synchronization of Multi-thread Lanes
Intel Corporation
0 cites
US118099052023
Local Memory Sharing Between Kernels
Intel Corporation
0 cites
US118034762023
Instruction Prefetch Mechanism
INTEL CORPORATION
0 cites
US117626962023
Hybrid Low Power Homogenous Grapics Processing Units
INTEL CORPORATION
0 cites
US117628042023
Scalar Core Integration
INTEL CORPORATION
0 cites
US117481302023
Virtualization and Multi-tenancy Support in Graphics Processors
INTEL CORPORATION
0 cites
US117483022023
Engine to Enable High Speed Context Switching via On-die Storage
INTEL CORPORATION
0 cites
US117267932023
Data Locality Enhancement for Graphics Processing Units
INTEL CORPORATION
0 cites
US117097932023
Graphics Processors and Graphics Processing Units Having Dot Product Accumulate Instruction for Hybrid Floating Point Format
Intel Corporation
0 cites
US117102692023
Position-based Rendering Apparatus and Method for Multi-die/gpu Graphics Processing
Intel Corporation
0 cites
US116881222023
Order Independent Asynchronous Compute and Streaming for Graphics
Intel Corporation
0 cites
US116762392023
Sparse Optimizations for a Matrix Accelerator Architecture
Intel Corporation
0 cites
US116693292023
Instructions and Logic for Vector Multiply Add with Zero Skipping
Intel Corporation
0 cites
US116694902023
Computing Efficient Cross Channel Operations in Parallel Computing Machines Using Systolic Arrays
INTEL CORPORATION
0 cites
US116637462023
Systolic Arithmetic on Sparse Data
Intel Corporation
0 cites
US116402972023
Instruction and Logic for Systolic Dot Product with Accumulate
Intel Corporation
0 cites
US116406932023
Dynamically Enabling Tiling in 3D Workloads
Intel Corporation
0 cites
US116361742023
Scalable Sparse Matrix Multiply Acceleration Using Systolic Arrays with Feedback Inputs
Intel Corporation
0 cites
US116252442023
Native Support for Execution of Get Exponent, Get Mantissa, and Scale Instructions Within a Graphics Processing Unit via Reuse of Fused Multiply-add Execution Unit Hardware Logic
Intel Corporation
0 cites
US116202562023
Systems and Methods for Improving Cache Efficiency and Utilization
Intel Corporation
0 cites
US115930692023
Use of a Single Instruction Set Architecture (ISA) Instruction for Vector Normalization
Intel Corporation
0 cites
US115939102023
Compute Optimization Mechanism for Deep Neural Networks
Intel Corporation
0 cites
US115798782023
Register Sharing Mechanism to Equally Allocate Disabled Thread Registers to Active Threads
Intel Corporation
0 cites
US115618282023
Graphics Systems and Methods for Accelerating Synchronization Using Fine Grain Dependency Check and Scheduling Optimizations Based on Available Shared Memory Space
Intel Corporation
0 cites
US115624612023
Compute Optimization Mechanism for Deep Neural Networks
Intel Corporation
0 cites