Sreenivas Mandava

6 Patents

• US125414602026

  Memory Transaction Queue Bypass Based on Configurable Address and Bandwidth Conditions

  Intel Corporation

  0 cites
• US124170422025

  Detection of Data Corruption in Memory Address Decode Circuitry

  Intel Corporation

  0 cites
• US123475072025

  Method and Apparatus for Memory Chip Row Hammer Threat Backpressure Signal and Host Side Response

  Intel Corporation

  0 cites
• US123216222025

  Deferred ECC (error Checking and Correction) Memory Initialization by Memory Scrub Hardware

  Intel Corporation

  0 cites
• US122357202025

  Adaptive Error Correction to Improve System Memory Reliability, Availability, and Serviceability (RAS)

  Intel Corporation

  0 cites
• US120993882024

  Temperature-based Runtime Variability in Victim Address Selection for Probabilistic Schemes for Row Hammer

  Intel Corporation

  0 cites