Patents/Inventors

Sreekanth G. Pai

CochinIN4 patents

4 Patents

US122100582025
Clock Gating for Power Reduction During Testing
Marvell Asia Pte Ltd
0 cites
US120256612024
Power-sensitive Scan-chain Testing
Marvell Asia Pte Ltd
0 cites
US117682392023
Method and Apparatus for Timing-annotated Scan-chain Testing Using Parallel Testbench
Marvell Asia Pte Ltd
0 cites
US116871472023
Reducing Leakage Power in Low-power Mode of an Integrated Circuit Device
Marvell Asia Pte, Ltd.
0 cites