Patents/Inventors

Sivananda K. Kanakasabapathy

Pleasanton, CAUS7 patents

6 Patents

US125503592026
Forming a Sacrificial Liner for Dual Channel Devices
Adeia Semiconductor Solutions LLC
0 cites
USRE0501742024
Structure and Process to Tuck Fin Tips Self-aligned to Gates
Tessera LLC
0 cites
US121069632024
Self Aligned Pattern Formation Post Spacer Etchback in Tight Pitch Configurations
Tessera LLC
0 cites
US118944622024
Forming a Sacrificial Liner for Dual Channel Devices
Adeia Semiconductor Solutions LLC
0 cites
US116705102023
Self Aligned Pattern Formation Post Spacer Etchback in Tight Pitch Configurations
Tessera LLC
0 cites
US116462212023
Self-aligned Pattern Formation for a Semiconductor Device
International Business Machines Corporation
0 cites