Siddharth Chouksey

14 Patents

• US125504012026

  Doped STI to Reduce Source/drain Diffusion for Germanium NMOS Transistors

  Intel Corporation

  0 cites
• US124143392025

  Formation of Gate Spacers for Strained PMOS Gate-all-around Transistor Structures

  Intel Corporation

  0 cites
• US123289272025

  Low Resistance and Reduced Reactivity Approaches for Fabricating Contacts and the Resulting Structures

  Intel Coporation

  0 cites
• US122727272025

  Gate-all-around Integrated Circuit Structures Having Embedded Gesnb Source or Drain Structures

  Intel Corporation

  0 cites
• US122665702025

  Self-aligned Interconnect Structures and Methods of Fabrication

  Intel Corporation

  0 cites
• US122552342025

  Integrated Circuit Structures Having Germanium-based Channels

  Intel Corporation

  0 cites
• US121991422025

  Neighboring Gate-all-around Integrated Circuit Structures Having Conductive Contact Stressor Between Epitaxial Source or Drain Regions

  Intel Corporation

  0 cites
• US121193872024

  Low Resistance Approaches for Fabricating Contacts and the Resulting Structures

  Intel Corporation

  0 cites
• US119905132024

  Gate-all-around Integrated Circuit Structures Having Embedded Gesnb Source or Drain Structures

  Intel Corporation

  0 cites
• US119232902024

  Halogen Treatment for NMOS Contact Resistance Improvement

  Intel Corporation

  0 cites
• US119234212024

  Integrated Circuit Structures Having Germanium-based Channels

  Intel Corporation

  0 cites
• US117356702023

  Non-selective Epitaxial Source/drain Deposition to Reduce Dopant Diffusion for Germanium NMOS Transistors

  Intel Corporation

  0 cites
• US116997562023

  Source/drain Diffusion Barrier for Germanium Nmos Transistors

  Intel Corporation

  0 cites
• US115750052023

  Asymmetrical Semiconductor Nanowire Field-effect Transistor

  Intel Corporation

  0 cites