Shubra Marwaha

10 Patents

• US124301282025

  Sharing Register File Usage Between Fused Processing Resources

  Intel Corporation

  0 cites
• US124057872025

  Utilizing Structured Sparsity in Systolic Arrays

  INTEL CORPORATION

  0 cites
• US120390012024

  Scalable Sparse Matrix Multiply Acceleration Using Systolic Arrays with Feedback Inputs

  Intel Corporation

  0 cites
• US120079352024

  Graphics Processors and Graphics Processing Units Having Dot Product Accumulate Instruction for Hybrid Floating Point Format

  Intel Corporation

  0 cites
• US120080672024

  Sparse Matrix Multiplication Acceleration Mechanism

  Intel Corporation

  0 cites
• US119778852024

  Utilizing Structured Sparsity in Systolic Arrays

  INTEL CORPORATION

  0 cites
• US119540632024

  Graphics Processors and Graphics Processing Units Having Dot Product Accumulate Instruction for Hybrid Floating Point Format

  Intel Corporation

  0 cites
• US117097932023

  Graphics Processors and Graphics Processing Units Having Dot Product Accumulate Instruction for Hybrid Floating Point Format

  Intel Corporation

  0 cites
• US116402972023

  Instruction and Logic for Systolic Dot Product with Accumulate

  Intel Corporation

  0 cites
• US116361742023

  Scalable Sparse Matrix Multiply Acceleration Using Systolic Arrays with Feedback Inputs

  Intel Corporation

  0 cites