10 Patents
- US125989322026Methods and Structures for Improving Etch Profile of Underlying Layers
Tokyo Electron Limited
0 cites - US125882622026Sacrificial Gate Capping Layer for Gate Protection During Source/drain Contact Opening
Tokyo Electron Limited
0 cites - US125686772026Method of Self-aligned Dielectric Wall Formation for Forksheet Application
Tokyo Electron Limited
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- US122372162025Method for Filling Recessed Features in Semiconductor Devices with a Low-resistivity Metal
Tokyo Electron Limited
0 cites - US120401762024Technologies for High Aspect Ratio Carbon Etching with Inserted Charge Dissipation Layer
Tokyo Electron Limited
0 cites - US120092112024Method for Highly Anisotropic Etching of Titanium Oxide Spacer Using Selective Top-deposition
Tokyo Electron Limited
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- US116519672023Non-atomic Layer Deposition (ALD) Method of Forming Sidewall Passivation Layer During High Aspect Ratio Carbon Layer Etch
Tokyo Electron Limited
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