Patents/Inventors

Sheng-en David Lin

Austin, TXUS1 patent

2 Patents

US123397012025
Insertion Delay and Area Tradeoff for Buffering Solution Selection in Clock Tree Synthesis
Cadence Design Systems, Inc.
0 cites
US123211932025
Hierarchically-aware Buffering for Clock Structures
Cadence Design Systems, Inc.
0 cites