22 Patents
- US124567022025Device, Method and System to Mitigate Stress on Hybrid Bonds in a Multi-tier Arrangement of Chiplets
Intel Corporation
0 cites - US124245432025Selective Interconnects in Back-end-of-line Metallization Stacks of Integrated Circuitry
Intel Corporation
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- US123157942025Skip Level Vias in Metallization Layers for Integrated Circuit Devices
Intel Corporation
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- US122887462025Skip Level Vias in Metallization Layers for Integrated Circuit Devices
Intel Corporation
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- US122668402025Waveguide Interconnects for Semiconductor Packages and Related Methods
Intel Corporation
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- US118308312023Semiconductor Package Including a Modular Side Radiating Waveguide Launcher
Intel Corporation
0 cites - US118240182023Heterogeneous Nested Interposer Package for IC Chips0 cites
- US117496492023Composite IC Chips Including a Chiplet Embedded Within Metallization Layers of a Host IC Chip
Intel Corporation
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- US115812382023Heat Spreading Layer Integrated Within a Composite IC Die Structure and Methods of Forming the Same
Intel Corporation
0 cites - 0 cites