8 Patents
- US123275992025Memory with Scan Chain Testing of Column Redundancy Logic and Multiplexing
QUALCOMM Incorporated
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- US120207662024Memory Circuit Architecture with Multiplexing Between Memory Banks
QUALCOMM INCORPORATED
0 cites - US119728342024Low Power and Robust Level-shifting Pulse Latch for Dual-power Memories
QUALCOMM Incorporated
0 cites - 0 cites
- US119356062024Memory with Scan Chain Testing of Column Redundancy Logic and Multiplexing
QUALCOMM Incorporated
0 cites - 0 cites