Shailesh Kumar Madisetti

6 Patents

• US126219792026

  Multi-tier Memory Structure with Graded Characteristics

  INTEL CORPORATION

  0 cites
• US126220182026

  Multi-layered or Graded Semiconductor Region in Thin Film Transistor (TFT) Structures

  INTEL CORPORATION

  0 cites
• US126220422026

  Multi-layered or Graded Gate Dielectric in Thin Film Transistor (TFT) Structures

  INTEL CORPORATION

  0 cites
• US126105822026

  Multi-layered Source and Drain Contacts for a Thin Film Transistor (TFT) Structure

  Intel Corporation

  0 cites
• US125988102026

  Co-doping of Thin Film Transistors

  INTEL CORPORATION

  0 cites
• US124329792025

  Gate Dielectric for Thin Film Oxide Transistors

  Intel Corporation

  0 cites