Sasikanth Avancha

7 Patents

• US124057872025

  Utilizing Structured Sparsity in Systolic Arrays

  INTEL CORPORATION

  0 cites
• US123996852025

  Systolic Array Having Support for Output Sparsity

  Intel Corporation

  0 cites
• US120390002024

  Matrix Operation Optimization Mechanism

  Intel Corporation

  0 cites
• US119778852024

  Utilizing Structured Sparsity in Systolic Arrays

  INTEL CORPORATION

  0 cites
• US116815292023

  Apparatuses, Methods, and Systems for Access Synchronization in a Shared Memory

  Intel Corporation

  0 cites
• US116693292023

  Instructions and Logic for Vector Multiply Add with Zero Skipping

  Intel Corporation

  0 cites
• US115934542023

  Matrix Operation Optimization Mechanism

  Intel Corporation

  0 cites