Patents/Inventors

Sanjay Subbarao

Irvine, CAUS30 patents

28 Patents

US126195502026
Storing a Logical-to-physical Mapping in NAND Memory
Micron Technology, Inc.
0 cites
US126195512026
Caching of Logical-to-physical Mapping Information in a Memory Sub-system
Micron Technology, Inc.
0 cites
US126138052026
Management of Programming Mode Transitions to Accommodate a Constant Size of Data Transfer Between a Host System and a Memory Sub-system
Micron Technology, Inc.
0 cites
US124988852025
Methods and Systems for Implementing Stream Data Updates
SK Hynix NAND Product Solutions Corp.
0 cites
US124988862025
Buffer Allocation for Reducing Block Transit Penalty
MICRON TECHNOLOGY, Inc.
0 cites
US124814632025
Multiple-pass Programming of Memory Cells Using Temporary Parity Generation
MICRON TECHNOLOGY, Inc.
0 cites
US122165412025
Block Failure Protection for Zone Memory System
Micron Technology, Inc.
0 cites
US121307482024
Caching of Logical-to-physical Mapping Information in a Memory Sub-system
Micron Technology, Inc.
0 cites
US121243802024
Storing a Logical-to-physical Mapping in NAND Memory
Micron Technology, Inc.
0 cites
US120795172024
Buffer Allocation for Reducing Block Transit Penalty
MICRON TECHNOLOGY, Inc.
0 cites
US120514792024
Memory Block Programming Using Defectivity Information
MICRON TECHNOLOGY, Inc.
0 cites
US120508092024
Multi-pass Data Programming in a Memory Sub-system Having Multiple Dies and Planes
Micron Technology, Inc.
0 cites
US120451682024
Timed Data Transfer Between a Host System and a Memory Sub-system
Micron Technology, Inc.
0 cites
US120017212024
Multiple-pass Programming of Memory Cells Using Temporary Parity Generation
MICRON TECHNOLOGY, Inc.
0 cites
US119220112024
Virtual Management Unit Scheme for Two-pass Programming in a Memory Sub-system
Micron Technology, Inc.
0 cites
US119144712024
Block Failure Protection for Zone Memory System
Micron Technology, Inc.
0 cites
US118682872024
Just-in-time (JIT) Scheduler for Memory Subsystems
Micron Technology, Inc.
0 cites
US117826432023
Partial Execution of a Write Command from a Host System
Micron Technology, Inc.
0 cites
US117828412023
Management of Programming Mode Transitions to Accommodate a Constant Size of Data Transfer Between a Host System and a Memory Sub-system
Micron Technology, Inc.
0 cites
US117554952023
Storing a Logical-to-physical Mapping in NAND Memory
Micron Technology, Inc.
0 cites
US117341892023
Caching of Logical-to-physical Mapping Information in a Memory Sub-system
Micron Technology, Inc.
0 cites
US117267032023
Extending Size of Memory Unit
Micron Technology, Inc.
0 cites
US117145622023
Journal Scheme for Two-pass Programming Memory Devices
Micron Technology, Inc.
0 cites
US117096322023
Input/output Size Control Between a Host System and a Memory Sub-system
Micron Technology, Inc.
0 cites
US116766792023
Two-layer Code with Low Parity Cost for Memory Sub-systems
Micron Technology, Inc.
0 cites
US116692722023
Predictive Data Transfer Based on Availability of Media Units in Memory Sub-systems
Micron Technology, Inc.
0 cites
US116403542023
Logical-to-physical Mapping of Data Groups with Data Locality
Micron Technology, Inc.
0 cites
US115737422023
Dynamic Data Placement for Collision Avoidance Among Concurrent Write Streams
Micron Technology, Inc.
0 cites