Sameer Chakravarthy Chillarige

2 Patents

• US124752882025

  Clock-based Test-point Flop Sharing in a Circuit Design

  Cadence Design Systems, Inc.

  0 cites
• US115924822023

  Scan Channel Slicing for Compression-mode Testing of Scan Chains

  CADENCE DESIGN SYSTEMS, Inc.

  0 cites