Robert John Gleixner

4 Patents

• US121317782024

  Triggering of Stronger Write Pulses in a Memory Device Based on Prior Read Operations

  Micron Technology, Inc.

  0 cites
• US120207432024

  Memory Device Architecture Using Multiple Physical Cells per Bit to Improve Read Margin and to Alleviate the Need for Managing Demarcation Read Voltages

  Micron Technology, Inc.

  0 cites
• US118237612023

  Pre-read in Opposite Polarity to Evaluate Read Margin

  Micron Technology, Inc.

  0 cites
• US116054182023

  Memory Device Architecture Using Multiple Physical Cells per Bit to Improve Read Margin and to Alleviate the Need for Managing Demarcation Read Voltages

  Micron Technology, Inc.

  0 cites