Patents/Inventors

Rishabh Mehandru

Portland, ORUS52 patents

61 Patents

US126158132026
Gate-all-around Integrated Circuit Structures Having Vertically Discrete Source or Drain Structures
Intel Corporation
0 cites
US126105272026
Integrated Circuit Structures Having Memory Access Transistor with Backside Contact
Intel Corporation
0 cites
US125884852026
Integrated Circuit Structures Having Airgaps for Backside Signal Routing or Power Delivery
Intel Corporation
0 cites
US125751512026
Gate-all-around Integrated Circuit Structures Having Doped Subfin
Intel Corporation
0 cites
US125074492025
Gate-all-around Integrated Circuit Structures Having Necked Feature
Intel Corporation
0 cites
US125016612025
Integrated Circuit Structures Having Differentiated Channel Sizing
Intel Corporation
0 cites
US124713622025
Integrated Circuit Structures Having Ultra-high Conductivity Global Routing
Intel Corporation
0 cites
US124262992025
Fin Shaping and Integrated Circuit Structures Resulting Therefrom
Intel Corporation
0 cites
US123494202025
Device, Method and System to Provide a Stressed Channel of a Transistor
Intel Corporation
0 cites
US123362782025
Gate-all-around Integrated Circuit Structures Having High Mobility
Intel Corporation
0 cites
US123175902025
Substrate-free Integrated Circuit Structures
Intel Corporation
0 cites
US123100442025
Vertical Integration Scheme and Circuit Elements Architecture for Area Scaling of Semiconductor Devices
Intel Corporation
0 cites
US122888102025
Backside Contact Structures and Fabrication for Metal on Both Sides of Devices
Intel Corporation
0 cites
US122888132025
Gate-all-around Integrated Circuit Structures Having Insulator Fin on Insulator Substrate
Intel Corporation
0 cites
US122888072025
Amorphization and Regrowth of Source-drain Regions from the Bottom-side of a Semiconductor Assembly
Intel Corporation
0 cites
US122551372025
Sideways Vias in Isolation Areas to Contact Interior Layers in Stacked Devices
Intel Corporation
0 cites
US122243262025
Contact Architecture for Capacitance Reduction and Satisfactory Contact Resistance
Intel Corporation
0 cites
US121990982025
Fin Doping and Integrated Circuit Structures Resulting Therefrom
Intel Corporation
0 cites
US121764292024
Wrap-around Contact Structures for Semiconductor Nanowires and Nanoribbons
Intel Corporation
0 cites
US121070852024
Interconnect Techniques for Electrically Connecting Source/drain Regions of Stacked Transistors
Intel Corporation
0 cites
US121007052024
Deep Trench via for Three-dimensional Integrated Circuit
Intel Corporation
0 cites
US121006232024
Vertically Stacked Finfets and Shared Gate Patterning
Intel Corporation
0 cites
US120574942024
Stacked Transistors
Intel Corporation
0 cites
US120338962024
Isolation Wall Stressor Structures to Improve Channel Stress and Their Methods of Fabrication
Intel Corporation
0 cites
US119963622024
Integrated Circuit Device with Crenellated Metal Trace Layout
Intel Corporation
0 cites
US119845062024
Field Effect Transistor Having a Gate Dielectric with a Dipole Layer and Having a Gate Stressor Layer
Intel Corporation
0 cites
US119424162024
Sideways Vias in Isolation Areas to Contact Interior Layers in Stacked Devices
Intel Corporation
0 cites
US119425262024
Integrated Circuit Contact Structures
Intel Corporation
0 cites
US119358912024
Non-silicon N-type and P-type Stacked Transistors for Integrated Circuit Devices
Intel Corporation
0 cites
US119359332024
Backside Contact Structures and Fabrication for Metal on Both Sides of Devices
Intel Corporation
0 cites
US119234122024
Sub-fin Leakage Reduction for Template Strained Materials
Intel Corporation
0 cites
US119014572024
Fin Shaping and Integrated Circuit Structures Resulting Therefrom
Intel Corporation
0 cites
US118942622024
Back Side Processing of Integrated Circuit Structures to Form Insulation Structure Between Adjacent Transistor Structures
Intel Corporation
0 cites
US118698902024
Stacked Transistors with Contact Last
Intel Corporation
0 cites
US118627022024
Gate-all-around Integrated Circuit Structures Having Insulator FIN on Insulator Substrate
Intel Corporation
0 cites
US118548942023
Integrated Circuit Device Structures and Double-sided Electrical Testing
Intel Corporation
0 cites
US118430522023
Transistor Contact Area Enhancement
Intel Corporation
0 cites
US118241072023
Wrap-around Contact Structures for Semiconductor Nanowires and Nanoribbons
Intel Corporation
0 cites
US118240972023
Contact Architecture for Capacitance Reduction and Satisfactory Contact Resistance
Intel Corporation
0 cites
US117989912023
Amorphization and Regrowth of Source-drain Regions from the Bottom-side of a Semiconductor Assembly
Intel Corporation
0 cites
US117988382023
Capacitance Reduction for Semiconductor Devices Based on Wafer Bonding
Intel Corporation
0 cites
US117423462023
Interconnect Techniques for Electrically Connecting Source/drain Regions of Stacked Transistors
Intel Corporation
0 cites
US117217352023
Thin Film Transistors Having U-shaped Features
Intel Corporation
0 cites
US117055182023
Isolation Schemes for Gate-all-around Transistor Devices
Intel Corporation
0 cites
US116887802023
Deep Source and Drain for Transistor Structures with Back-side Contact Metallization
Intel Corporation
0 cites
US116886372023
Wrap-around Contact Structures for Semiconductor Fins
Intel Corporation
0 cites
US116643772023
Forksheet Transistor Architectures
Intel Corporation
0 cites
US116643732023
Isolation Walls for Vertically Stacked Transistor Structures
Intel Corporation
0 cites
US116581832023
Metallization Structures Under a Semiconductor Device Layer
Intel Corporation
0 cites
US116582212023
Backside Contact Structures and Fabrication for Metal on Both Sides of Devices
Intel Corporation
0 cites
US116580722023
Vertically Stacked Transistors in a Fin
Intel Corporation
0 cites
US116521072023
Substrate-less Finfet Diode Architectures with Backside Metal Contact and Subfin Regions
Intel Corporation
0 cites
US116409612023
III-V Source/drain in Top NMOS Transistors for Low Temperature Stacked Transistor Contacts
Intel Corporation
0 cites
US116160562023
Vertical Diode in Stacked Transistor Architecture
Intel Corporation
0 cites
US116160602023
Techniques for Forming Gate Structures for Transistors Arranged in a Stacked Configuration on a Single Fin Structure
Intel Corporation
0 cites
US116160152023
Integrated Circuit Device with Back-side Interconnection to Deep Source/drain Semiconductor
Intel Corporation
0 cites
US116055562023
Back Side Processing of Integrated Circuit Structures to Form Insulation Structure Between Adjacent Transistor Structures
Intel Corporation
0 cites
US116006962023
Sub-fin Leakage Reduction for Template Strained Materials
Intel Corporation
0 cites
US115737982023
Stacked Transistors with Different Gate Lengths in Different Device Strata
Intel Corporation
0 cites
US115576762023
Device, Method and System to Provide a Stressed Channel of a Transistor
Intel Corporation
0 cites
US115521042023
Stacked Transistors with Dielectric Between Channels of Different Device Strata
Intel Corporation
0 cites