Rakesh Kumar Gupta

6 Patents

• US126036572026

  Reducing Non-linearity in a Digital-to-time Converter (DTC) Due to Unequal Successive Input Codes Specifying Respective Delays

  Shaoxing Yuanfang Semiconductor Co., Ltd.

  0 cites
• US124618602025

  Physical Address Based Set Partitioning

  QUALCOMM Incorporated

  0 cites
• US121492552024

  Generating Divided Signals from Phase-locked Loop (PLL) Output When Reference Clock Is Unavailable

  Shaoxing Yuanfang Semiconductor Co., Ltd.

  0 cites
• US120260282024

  Preventing Reverse-current Flow When an Integrated Circuit Operates Using Power Supplies of Different Magnitudes

  Shaoxing Yuanfang Semiconductor Co., Ltd.

  0 cites
• US119679652024

  Generating Divided Signals from Phase-locked Loop (PLL) Output When Reference Clock Is Unavailable

  Shaoxing Yuanfang Semiconductor Co., Ltd.

  0 cites
• US115884892023

  Obtaining Lock in a Phase-locked Loop (PLL) Upon Being Out of Phase-lock

  Shaoxing Yuanfang Semiconductor Co., Ltd.

  0 cites