Patents/Inventors

Rajat Agarwal

Portland, ORUS32 patents

29 Patents

US125788892026
Apparatus, Device, and Method for a Memory Controller, Memory Controller, and System
Intel Corporation
0 cites
US125636512026
Methods and Apparatus to Supply Power to LED Circuitry
TEXAS INSTRUMENTS INCORPORATED
0 cites
US125493312026
Memory Bus Integrity and Data Encryption (IDE)
Intel Corporation
0 cites
US124300572025
Dynamic Multilevel Memory System
Intel Corporation
0 cites
US123867482025
Selective Fill for Logical Control Over Hardware Multilevel Memory
Intel Corporation
0 cites
US123732872025
Distribution of Error Checking and Correction (ECC) Bits to Allocate ECC Bits for Metadata
Intel Corporation
0 cites
US123608472025
Adaptive Internal Error Scrubbing and Error Handling
Intel Corporation
0 cites
US123554112025
Nonlinearity Cancellation Circuit for Active Filters
TEXAS INSTRUMENTS INCORPORATED
0 cites
US123477832025
Interconnect Architecture with Silicon Interposer and EMIB
Intel Corporation
0 cites
US123274522025
Universal Retrofit of Controlled Locking Access in a Locker Solution Method and System
HOLLMAN, Inc.
0 cites
US122713052025
Two-level Main Memory Hierarchy Management
Intel Corporation
0 cites
US122597772025
Uncorrectable Memory Error Prediction
Intel Corporation
0 cites
US122542032025
Message Authentication Galois Integrity and Correction (MAGIC) for Lightweight Row Hammer Mitigation
Intel Corporation
0 cites
US122423422025
Fast Memory ECC Error Correction
Intel Corporation
0 cites
US122357202025
Adaptive Error Correction to Improve System Memory Reliability, Availability, and Serviceability (RAS)
Intel Corporation
0 cites
US122382212025
Cryptographic System Memory Management
Intel Corporation
0 cites
US121243712024
Apparatus and Method to Reduce Bandwidth and Latency Overheads of Probabilistic Caches
Intel Corporation
0 cites
US120668882024
Efficient Security Metadata Encoding in Error Correcting Code (ECC) Memory Without Dedicated ECC Bits
Intel Corporation
0 cites
US119950062024
Algebraic and Deterministic Memory Authentication and Correction with Coupled Cacheline Metadata
Intel Corporation
0 cites
USD10272162024
Secure Work Pod
Hollman Family Advisors, LLC
0 cites
USD10272182024
Secure Work Pod
Hollman Family Advisors, LLC
0 cites
US119662862024
Read Retry to Selectively Disable On-die ECC
Intel Corporation
0 cites
US119609002024
Technologies for Fast Booting with Error-correcting Code Memory
Intel Corporation
0 cites
US119281242024
Artificial Intelligence (AI) Based Data Processing
ACCENTURE GLOBAL SOLUTIONS LIMITED
0 cites
US119012992024
Interconnect Architecture with Silicon Interposer and EMIB
Intel Corporation
0 cites
US118373142023
Undo and Redo of Soft Post Package Repair
SK Hynix NAND Product Solutions Corp.
0 cites
US115800292023
Memory System, Computing System, and Methods Thereof for Cache Invalidation with Dummy Address Space
Intel Corporation
0 cites
US115678772023
Memory Utilized as Both System Memory and Near Memory
Intel Corporation
0 cites
US115575412023
Interconnect Architecture with Silicon Interposer and EMIB
Intel Corporation
0 cites