Prateek Kumar Rai

3 Patents

• US125114622025

  Physical Awareness of Test-point Sharing in a Circuit Design

  Cadence Design Systems, Inc.

  0 cites
• US124752882025

  Clock-based Test-point Flop Sharing in a Circuit Design

  Cadence Design Systems, Inc.

  0 cites
• US119478872024

  Test-point Flop Sharing with Improved Testability in a Circuit Design

  Cadence Design Systems, Inc.

  0 cites