Patents/Inventors

Paul Gutwin

Williston, VTUS18 patents

17 Patents

US125686512026
Semiconductor Structure Having Stacked Gates and Method of Manufacture Thereof
Tokyo Electron Limited
0 cites
US125573772026
Inverted Cross-couple for Top-tier FET for Multi-tier Gate-on-gate 3DI
Tokyo Electron Limited
0 cites
US124462912025
Inverted Top-tier FET for Multi-tier Gate-on-gate 3-dimension Integration (3di)
TOKYO ELECTRON LIMITED
0 cites
US124143672025
Tapered Device for Lateral Gate All Around Devices
Tokyo Electron Limited
0 cites
US123362742025
Self-aligned Method for Vertical Recess for 3D Device Integration
Tokyo Electron Limited
0 cites
US122242812025
Interdigitated Device Stack
TOKYO ELECTRON LIMITED
0 cites
US122181352025
Wiring in Diffusion Breaks in an Integrated Circuit
Tokyo Electron Limited
0 cites
US121762932024
Inter-tier Power Delivery Network (PDN) for Dense Gate-on-gate 3D Logic Integration
TOKYO ELECTRON LIMITED
0 cites
US120516382024
Integrated High Efficiency Transistor Cooling
Tokyo Electron Limited
0 cites
US120028622024
Inter-level Handshake for Dense 3D Logic Integration
Tokyo Electron Limited
0 cites
US119618022024
Power-tap Pass-through to Connect a Buried Power Rail to Front-side Power Distribution Network
Tokyo Electron Limited
0 cites
US119233642024
Double Cross-couple for Two-row Flip-flop Using CFET
Tokyo Electron Limited
0 cites
US118308522023
Multi-tier Backside Power Delivery Network for Dense Gate-on-gate 3D Logic
TOKYO ELECTRON LIMITED
0 cites
US117641132023
Method of 3D Logic Fabrication to Sequentially Decrease Processing Temperature and Maintain Material Thermal Thresholds
Tokyo Electron Limited
0 cites
US117642662023
Three-dimensional Semiconductor Device
Tokyo Electron Limited
0 cites
US117231872023
Three-dimensional Memory Cell Structure
Tokyo Electron Limited
0 cites
US115812422023
Integrated High Efficiency Gate on Gate Cooling
Tokyo Electron Limited
0 cites