65 Patents
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- US125060592025Vertically Spaced Intra-level Interconnect Line Metallization for Integrated Circuit Devices
Intel Corporation
0 cites - US124462042025SRAM with P-type Access Transistors and Complementary Field-effect Transistor Technology
Intel Corporation
0 cites - US123693992025Gate-to-gate Isolation for Stacked Transistor Architecture via Selective Dielectric Deposition Structure
INTEL CORPORATION
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- US123100442025Vertical Integration Scheme and Circuit Elements Architecture for Area Scaling of Semiconductor Devices
Intel Corporation
0 cites - US122888102025Backside Contact Structures and Fabrication for Metal on Both Sides of Devices
Intel Corporation
0 cites - US122551372025Sideways Vias in Isolation Areas to Contact Interior Layers in Stacked Devices
Intel Corporation
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- US121991432025Gate-all-around Integrated Circuit Structures Having Removed Substrate
Intel Corporation
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- US121070852024Interconnect Techniques for Electrically Connecting Source/drain Regions of Stacked Transistors
Intel Corporation
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- US121007612024Wrap-around Source/drain Method of Making Contacts for Backside Metals
Intel Corporation
0 cites - US121007622024Wrap-around Source/drain Method of Making Contacts for Backside Metals
Intel Corporation
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- US119488742024Vertically Spaced Intra-level Interconnect Line Metallization for Integrated Circuit Devices
Intel Corporation
0 cites - US119424162024Sideways Vias in Isolation Areas to Contact Interior Layers in Stacked Devices
Intel Corporation
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- US119358912024Non-silicon N-type and P-type Stacked Transistors for Integrated Circuit Devices
Intel Corporation
0 cites - US119359332024Backside Contact Structures and Fabrication for Metal on Both Sides of Devices
Intel Corporation
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- US118942622024Back Side Processing of Integrated Circuit Structures to Form Insulation Structure Between Adjacent Transistor Structures
Intel Corporation
0 cites - US118943722024Stacked Trigate Transistors with Dielectric Isolation and Process for Forming Such
Intel Corporation
0 cites - US118698942024Metallization Structures for Stacked Device Connectivity and Their Methods of Fabrication
Intel Corporation
0 cites - US118548942023Integrated Circuit Device Structures and Double-sided Electrical Testing
Intel Corporation
0 cites - US118309332023Gate-all-around Integrated Circuit Structures Having Depopulated Channel Structures Using Bottom-up Oxidation Approach
Intel Corporation
0 cites - US117988382023Capacitance Reduction for Semiconductor Devices Based on Wafer Bonding
Intel Corporation
0 cites - US117768982023Sidewall Interconnect Metallization Structures for Integrated Circuit Devices
Intel Corporation
0 cites - US117698142023Device Including Air Gapping of Gate Spacers and Other Dielectrics and Process for Providing Such
Intel Corporation
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- US117642632023Gate-all-around Integrated Circuit Structures Having Depopulated Channel Structures Using Multiple Bottom-up Oxidation Approaches
Intel Corporation
0 cites - US117496492023Composite IC Chips Including a Chiplet Embedded Within Metallization Layers of a Host IC Chip
Intel Corporation
0 cites - US117423462023Interconnect Techniques for Electrically Connecting Source/drain Regions of Stacked Transistors
Intel Corporation
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- US116996372023Vertically Stacked Transistor Devices with Isolation Wall Structures Containing an Electrical Conductor
Intel Corporation
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- US116769662023Stacked Transistors Having Device Strata with Different Channel Widths
Intel Corporation
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- US116582212023Backside Contact Structures and Fabrication for Metal on Both Sides of Devices
Intel Corporation
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- US116409612023III-V Source/drain in Top NMOS Transistors for Low Temperature Stacked Transistor Contacts
Intel Corporation
0 cites - US116160152023Integrated Circuit Device with Back-side Interconnection to Deep Source/drain Semiconductor
Intel Corporation
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- US116055562023Back Side Processing of Integrated Circuit Structures to Form Insulation Structure Between Adjacent Transistor Structures
Intel Corporation
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- US115944522023Techniques for Revealing a Backside of an Integrated Circuit Device, and Associated Configurations
Intel Corporation
0 cites - US115945242023Fabrication and Use of Through Silicon Vias on Double Sided Interconnect Device
Intel Corporation
0 cites - US115945332023Stacked Trigate Transistors with Dielectric Isolation Between First and Second Semiconductor Fins
Intel Corporation
0 cites - US115737982023Stacked Transistors with Different Gate Lengths in Different Device Strata
Intel Corporation
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- US115521042023Stacked Transistors with Dielectric Between Channels of Different Device Strata
Intel Corporation
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