21 Patents
- US125987342026Method of Making 3D Memory Stacking Formation with High Circuit Density
Tokyo Electron Limited
0 cites - US1253852020263D High Density Self-aligned Nanosheet Device Formation with Efficient Layout and Design
Tokyo Electron Limited
0 cites - US1250744720253D Advanced Transistor Architecture Integrated with Source/drain Spider Design
Tokyo Electron Limited
0 cites - US1250160220253D Hybrid Memory Using Horizontally Oriented Conductive Dielectric Channel Regions
Tokyo Electron Limited
0 cites - US124647042025Three-dimensional Plurality of N Horizontal Memory Cells with Enhanced High Performance Circuit Density
Tokyo Electron Limited
0 cites - 0 cites
- US124396412025Compact 3D Design and Connections with Optimum 3D Transistor Stacking
Tokyo Electron Limited
0 cites - 0 cites
- US123494242025Epitaxial Semiconductor 3D Horizontal Nano Sheet with High Mobility 2D Material Channel
Tokyo Electron Limited
0 cites - 0 cites
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- US122182442025Vertical Transistor Structures and Methods Utilizing Selective Formation
TOKYO ELECTRON LIMITED
0 cites - US121912102025Formation of High Density 3D Circuits with Enhanced 3D Conductivity
Tokyo Electron Limited
0 cites - US1217624920243D Nano Sheet Method Using 2D Material Integrated with Conductive Oxide for High Performance Devices
TOKYO ELECTRON LIMITED
0 cites - 0 cites
- US1213338720243D Memory with Conductive Dielectric Channel Integrated with Logic Access Transistors
Tokyo Electron Limited
0 cites - US121144802024Method of Making of Plurality of 3D Vertical Logic Elements Integrated with 3D Memory
Tokyo Electron Limited
0 cites - US1206820520243D High Density Compact Metal First Approach for Hybrid Transistor Designs Without Using Epitaxial Growth
TOKYO ELECTRON LIMITED
0 cites - 0 cites
- US118308762023Three-dimensional Device with Self-aligned Vertical Interconnection
Tokyo Electron Limited
0 cites - 0 cites