20 Patents
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- US124777982025Semiconductor Device Including a Superlattice and Enriched Silicon 28 Epitaxial Layer
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0 cites - US123225942025Method for Making Semiconductor Device Including a Superlattice and Enriched Silicon 28 Epitaxial Layer
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0 cites - US123157222025Method for Making a Radio Frequency Silicon-on-insulator (RFSOI) Wafer Including a Superlattice
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0 cites - US123157232025Method for Making Semiconductor Device with Selective Etching of Superlattice to Accumulate Non-semiconductor Atoms
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0 cites - US121991482025Semiconductor Device Including Superlattice with O18 Enriched Monolayers
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0 cites - US121911602025Method for Making a Semiconductor Superlattices with Different Non-semiconductor Thermal Stabilities
ATOMERA INCORPORATED
0 cites - US121426412024Method for Making Gate-all-around (GAA) Device Including a Superlattice
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0 cites - US121193802024Method for Making Semiconductor Device Including Superlattice with Oxygen and Carbon Monolayers
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0 cites - US120464702024Method for Making Semiconductor Device Including a Superlattice and Enriched Silicon 28 Epitaxial Layer
ATOMERA INCORPORATED
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- US119234182024Semiconductor Device Including a Superlattice and Enriched Silicon 28 Epitaxial Layer
ATOMERA INCORPORATED
0 cites - US118483562023Method for Making Semiconductor Device Including Superlattice with Oxygen and Carbon Monolayers
ATOMERA INCORPORATED
0 cites - US118376342023Semiconductor Device Including Superlattice with Oxygen and Carbon Monolayers
ATOMERA INCORPORATED
0 cites - US118107842023Method for Making Semiconductor Device Including a Superlattice and Enriched Silicon 28 Epitaxial Layer
ATOMERA INCORPORATED
0 cites - US117283852023Semiconductor Device Including Superlattice with O 18 Enriched Monolayers
ATOMERA INCORPORATED
0 cites - US117215462023Method for Making Semiconductor Device with Selective Etching of Superlattice to Accumulate Non-semiconductor Atoms
ATOMERA INCORPORATED
0 cites - US116827122023Method for Making Semiconductor Device Including Superlattice with O18 Enriched Monolayers
ATOMERA INCORPORATED
0 cites - US116644272023Vertical Semiconductor Device with Enhanced Contact Structure and Associated Methods
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0 cites - US116315842023Method for Making Semiconductor Device with Selective Etching of Superlattice to Define Etch Stop Layer
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